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Rename SCFF to CCFF, configuration chain flip flop

This commit is contained in:
AurelienUoU 2019-09-26 11:32:57 -06:00
parent e5faeb1400
commit 056219f180
21 changed files with 154 additions and 154 deletions
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28
vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp
View File

@ -286,14 +286,14 @@ size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib,
}
/************************************************************************
* A function to check the port map of SCFF circuit model
* A function to check the port map of CCFF circuit model
***********************************************************************/
size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib,
size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
size_t num_err = 0;
/* Check the type of circuit model */
VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.model_type(circuit_model));
VTR_ASSERT(SPICE_MODEL_CCFF == circuit_lib.model_type(circuit_model));
/* Check if we have D, Set and Reset */
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
@ -404,9 +404,9 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
* 2. Circuit models have unique prefix
* 3. Check IOPADs have input and output ports
* 4. Check MUXes has been defined and has input and output ports
* 5. We must have at least one SRAM or SCFF
* 5. We must have at least one SRAM or CCFF
* 6. SRAM must have at least an input and an output ports
* 7. SCFF must have at least a clock, an input and an output ports
* 7. CCFF must have at least a clock, an input and an output ports
* 8. FF must have at least a clock, an input and an output ports
* 9. LUT must have at least an input, an output and a SRAM ports
* 10. We must have default circuit models for these types: MUX, channel wires and wires
@ -456,13 +456,13 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) {
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required);
/* 5. We must have at least one SRAM or SCFF */
/* 5. We must have at least one SRAM or CCFF */
if ( ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SRAM).size())
&& ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SCFF).size()) ) {
&& ( 0 == circuit_lib.models_by_type(SPICE_MODEL_CCFF).size()) ) {
vpr_printf(TIO_MESSAGE_ERROR,
"At least one %s or %s circuit model is required!\n",
CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)],
CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SCFF)]);
CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_CCFF)]);
/* Incremental the counter for errors */
num_err++;
}
@ -474,13 +474,13 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) {
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SRAM, sram_port_types_required);
/* 7. SCFF must have at least a clock, an input and an output ports*/
std::vector<enum e_spice_model_port_type> scff_port_types_required;
scff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK);
scff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
scff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
/* 7. CCFF must have at least a clock, an input and an output ports*/
std::vector<enum e_spice_model_port_type> ccff_port_types_required;
ccff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK);
ccff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
ccff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SCFF, scff_port_types_required);
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_CCFF, ccff_port_types_required);
/* 8. FF must have at least a clock, an input and an output ports*/
std::vector<enum e_spice_model_port_type> ff_port_types_required;

2
vpr7_x2p/libarchfpga/SRC/check_circuit_library.h
View File

@ -71,7 +71,7 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary&
size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib,
size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,

4
vpr7_x2p/libarchfpga/SRC/circuit_library.cpp
View File

@ -612,7 +612,7 @@ std::vector<CircuitPortId> CircuitLibrary::model_global_ports_by_type(const Circ
}
/* Recursively find all the global ports in the circuit model / sub circuit_model
* but ignore all the SRAM and SCFF, which are configuration memories
* but ignore all the SRAM and CCFF, which are configuration memories
*/
std::vector<CircuitPortId> CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id,
const enum e_spice_model_port_type& type,
@ -621,7 +621,7 @@ std::vector<CircuitPortId> CircuitLibrary::model_global_ports_by_type(const Circ
std::vector<enum e_spice_model_type> ignore_list;
if (true == ignore_config_memories) {
ignore_list.push_back(SPICE_MODEL_SRAM);
ignore_list.push_back(SPICE_MODEL_SCFF);
ignore_list.push_back(SPICE_MODEL_CCFF);
}
return model_global_ports_by_type(model_id, type, recursive, ignore_list);
}

4
vpr7_x2p/libarchfpga/SRC/circuit_types.h
View File

@ -66,7 +66,7 @@ enum e_spice_model_type {
SPICE_MODEL_FF,
SPICE_MODEL_SRAM,
SPICE_MODEL_HARDLOGIC,
SPICE_MODEL_SCFF,
SPICE_MODEL_CCFF,
SPICE_MODEL_IOPAD,
SPICE_MODEL_INVBUF,
SPICE_MODEL_PASSGATE,
@ -74,7 +74,7 @@ enum e_spice_model_type {
NUM_CIRCUIT_MODEL_TYPES
};
/* Strings correspond to each port type */
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_TYPES> CIRCUIT_MODEL_TYPE_STRING = {{"CHAN_WIRE", "WIRE", "MUX", "LUT", "FF", "SRAM", "HARDLOGIC", "SCFF", "IOPAD", "INVBUF", "PASSGATE", "GATE"}};
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_TYPES> CIRCUIT_MODEL_TYPE_STRING = {{"CHAN_WIRE", "WIRE", "MUX", "LUT", "FF", "SRAM", "HARDLOGIC", "CCFF", "IOPAD", "INVBUF", "PASSGATE", "GATE"}};
enum e_spice_model_design_tech {
SPICE_MODEL_DESIGN_CMOS,

4
vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
View File

@ -915,7 +915,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
} else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"hard_logic")) {
spice_model->type = SPICE_MODEL_HARDLOGIC;
} else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"sff")) {
spice_model->type = SPICE_MODEL_SCFF;
spice_model->type = SPICE_MODEL_CCFF;
} else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"iopad")) {
spice_model->type = SPICE_MODEL_IOPAD;
} else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"inv_buf")) {
@ -1417,7 +1417,7 @@ static void check_spice_models(int num_spice_model,
}
}
/* Check scan-chain dff has input and output, clock ports*/
if (SPICE_MODEL_SCFF == spice_models[i].type) {
if (SPICE_MODEL_CCFF == spice_models[i].type) {
has_sram = 1;
has_clock_port = 0;
has_in_port = 0;

10
vpr7_x2p/libarchfpga/SRC/spice_types.h
View File

@ -476,12 +476,12 @@ struct s_mem_bank_info {
};
/* Scan-chain Flip-flops information */
typedef struct s_scff_info t_scff_info;
struct s_scff_info {
typedef struct s_ccff_info t_ccff_info;
struct s_ccff_info {
t_spice_model* mem_model; /* SPICE model of a memory bit */
int num_mem_bit; /* Number of memory bits in total */
int num_scff; /* Number of Scan-chain flip-flops */
/* TODO: More to be added, SCFF support is naive now */
int num_ccff; /* Number of Scan-chain flip-flops */
/* TODO: More to be added, CCFF support is naive now */
};
/* Standalone SRAMs information */
@ -495,7 +495,7 @@ struct s_standalone_sram_info {
struct s_sram_orgz_info {
enum e_sram_orgz type;
t_mem_bank_info* mem_bank_info; /* Only be allocated when orgz type is memory bank */
t_scff_info* scff_info; /* Only be allocated when orgz type is scan-chain */
t_ccff_info* ccff_info; /* Only be allocated when orgz type is scan-chain */
t_standalone_sram_info* standalone_sram_info; /* Only be allocated when orgz type is standalone */
/* Head of configuration bits,

18
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c
View File

@ -270,7 +270,7 @@ int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model,
case SPICE_MODEL_FF:
case SPICE_MODEL_SRAM:
case SPICE_MODEL_HARDLOGIC:
case SPICE_MODEL_SCFF:
case SPICE_MODEL_CCFF:
case SPICE_MODEL_IOPAD:
return count_num_sram_bits_one_generic_spice_model(cur_spice_model);
default:
@ -336,7 +336,7 @@ int count_num_mode_bits_one_spice_model(t_spice_model* cur_spice_model) {
case SPICE_MODEL_FF:
case SPICE_MODEL_SRAM:
case SPICE_MODEL_HARDLOGIC:
case SPICE_MODEL_SCFF:
case SPICE_MODEL_CCFF:
case SPICE_MODEL_IOPAD:
return count_num_mode_bits_one_generic_spice_model(cur_spice_model);
default:
@ -528,7 +528,7 @@ int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model,
case SPICE_MODEL_FF:
case SPICE_MODEL_SRAM:
case SPICE_MODEL_HARDLOGIC:
case SPICE_MODEL_SCFF:
case SPICE_MODEL_CCFF:
case SPICE_MODEL_IOPAD:
/* Other block, we just count the number SRAM ports defined by user */
num_reserved_conf_bits = 0;
@ -829,7 +829,7 @@ int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model,
case SPICE_MODEL_FF:
case SPICE_MODEL_SRAM:
case SPICE_MODEL_HARDLOGIC:
case SPICE_MODEL_SCFF:
case SPICE_MODEL_CCFF:
case SPICE_MODEL_IOPAD:
return count_num_conf_bits_one_generic_spice_model(cur_spice_model, cur_sram_orgz_type);
default:
@ -919,7 +919,7 @@ int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc,
/* add configuration bits of a MUX to linked-list
* when SRAM organization type is scan-chain */
void
add_mux_scff_conf_bits_to_llist(int mux_size,
add_mux_ccff_conf_bits_to_llist(int mux_size,
t_sram_orgz_info* cur_sram_orgz_info,
int num_mux_sram_bits, int* mux_sram_bits,
t_spice_model* mux_spice_model) {
@ -1134,7 +1134,7 @@ add_mux_conf_bits_to_llist(int mux_size,
switch (cur_sram_orgz_info->type) {
case SPICE_SRAM_STANDALONE:
case SPICE_SRAM_SCAN_CHAIN:
add_mux_scff_conf_bits_to_llist(mux_size, cur_sram_orgz_info,
add_mux_ccff_conf_bits_to_llist(mux_size, cur_sram_orgz_info,
num_mux_sram_bits, mux_sram_bits,
mux_spice_model);
break;
@ -1152,9 +1152,9 @@ add_mux_conf_bits_to_llist(int mux_size,
return;
}
/* Add SCFF configutration bits to a linked list*/
/* Add CCFF configutration bits to a linked list*/
static
void add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info,
void add_sram_ccff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info,
int num_sram_bits, int* sram_bits) {
int ibit, cur_mem_bit;
t_conf_bit** sram_bit = NULL;
@ -1304,7 +1304,7 @@ add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index,
switch (cur_sram_orgz_info->type) {
case SPICE_SRAM_STANDALONE:
case SPICE_SRAM_SCAN_CHAIN:
add_sram_scff_conf_bits_to_llist(cur_sram_orgz_info,
add_sram_ccff_conf_bits_to_llist(cur_sram_orgz_info,
num_sram_bits, sram_bits);
break;
case SPICE_SRAM_MEMORY_BANK:

10
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
View File

@ -347,17 +347,17 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib,
}
case SPICE_SRAM_SCAN_CHAIN:
/* Two types of ports are available:
* (1) Head of a chain of Scan-chain Flip-Flops (SCFFs), enabled by port type of INPUT
* (2) Tail of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of OUTPUT
* (1) Head of a chain of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT
* (2) Tail of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT
* +------+ +------+ +------+
* Head --->| SCFF |--->| SCFF |--->| SCFF |---> Tail
* Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail
* +------+ +------+ +------+
*/
if (SPICE_MODEL_PORT_INPUT == port_type) {
port_name += std::string("scff_head");
port_name += std::string("ccff_head");
} else {
VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type );
port_name += std::string("scff_tail");
port_name += std::string("ccff_tail");
}
break;
case SPICE_SRAM_MEMORY_BANK:

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c
View File

@ -344,7 +344,7 @@ void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz,
break;
case SPICE_SRAM_SCAN_CHAIN:
vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit scan-chain organization...\n");
if (SPICE_MODEL_SCFF != cur_sram_inf_orgz->spice_model->type) {
if (SPICE_MODEL_CCFF != cur_sram_inf_orgz->spice_model->type) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Scan-chain SRAM organization requires a SPICE model(type=sff)!\n",
__FILE__, __LINE__);
exit(1);

60
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -1094,7 +1094,7 @@ char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type)
case SPICE_MODEL_IOPAD:
ret = "iopad";
break;
case SPICE_MODEL_SCFF:
case SPICE_MODEL_CCFF:
ret = "Scan-chain Flip-flop";
break;
default:
@ -2220,7 +2220,7 @@ void check_sram_spice_model_ports(t_spice_model* cur_spice_model,
}
void check_ff_spice_model_ports(t_spice_model* cur_spice_model,
boolean is_scff) {
boolean is_ccff) {
int iport;
int num_input_ports;
t_spice_model_port** input_ports = NULL;
@ -2232,22 +2232,22 @@ void check_ff_spice_model_ports(t_spice_model* cur_spice_model,
int num_err = 0;
/* Check the type of SPICE model */
if (FALSE == is_scff) {
if (FALSE == is_ccff) {
assert(SPICE_MODEL_FF == cur_spice_model->type);
} else {
assert(SPICE_MODEL_SCFF == cur_spice_model->type);
assert(SPICE_MODEL_CCFF == cur_spice_model->type);
}
/* Check if we have D, Set and Reset */
input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, FALSE);
if (TRUE == is_scff) {
if (TRUE == is_ccff) {
if (1 > num_input_ports) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL should at least have an input port!\n",
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL should at least have an input port!\n",
__FILE__, __LINE__);
num_err++;
}
for (iport = 0; iport < num_input_ports; iport++) {
if (1 != input_ports[iport]->size) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL: each input port with size 1!\n",
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL: each input port with size 1!\n",
__FILE__, __LINE__);
num_err++;
}
@ -2269,20 +2269,20 @@ void check_ff_spice_model_ports(t_spice_model* cur_spice_model,
/* Check if we have clock */
clock_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_ports, FALSE);
if (1 > num_clock_ports) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|SCFF] SPICE MODEL should have at least 1 clock port!\n",
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|CCFF] SPICE MODEL should have at least 1 clock port!\n",
__FILE__, __LINE__);
num_err++;
}
for (iport = 0; iport < num_clock_ports; iport++) {
if (1 != clock_ports[iport]->size) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|SCFF] SPICE MODEL: 1 clock port with size 1!\n",
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|CCFF] SPICE MODEL: 1 clock port with size 1!\n",
__FILE__, __LINE__);
num_err++;
}
}
/* Check if we have output */
output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_ports, TRUE);
if (FALSE == is_scff) {
if (FALSE == is_ccff) {
if (1 != output_ports[0]->size) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL: each output port with size 1!\n",
__FILE__, __LINE__);
@ -2290,12 +2290,12 @@ void check_ff_spice_model_ports(t_spice_model* cur_spice_model,
}
} else {
if (2 != num_output_ports) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL should have 2 output ports!\n",
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL should have 2 output ports!\n",
__FILE__, __LINE__);
num_err++;
for (iport = 0; iport < num_output_ports; iport++) {
if (1 != output_ports[iport]->size) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL: the output port (%s) should have a size of 1!\n",
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL: the output port (%s) should have a size of 1!\n",
__FILE__, __LINE__, output_ports[iport]->prefix);
num_err++;
}
@ -2462,11 +2462,11 @@ void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info) {
return;
}
t_scff_info* alloc_one_scff_info() {
return (t_scff_info*)my_malloc(sizeof(t_scff_info));
t_ccff_info* alloc_one_ccff_info() {
return (t_ccff_info*)my_malloc(sizeof(t_ccff_info));
}
void free_one_scff_info(t_scff_info* scff_info) {
void free_one_ccff_info(t_ccff_info* ccff_info) {
return;
}
@ -2501,23 +2501,23 @@ void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info,
return;
}
void init_scff_info(t_scff_info* cur_scff_info,
void init_ccff_info(t_ccff_info* cur_ccff_info,
t_spice_model* cur_mem_model) {
assert(NULL != cur_scff_info);
assert(NULL != cur_ccff_info);
assert(NULL != cur_mem_model);
cur_scff_info->mem_model = cur_mem_model;
cur_scff_info->num_mem_bit = 0;
cur_scff_info->num_scff = 0;
cur_ccff_info->mem_model = cur_mem_model;
cur_ccff_info->num_mem_bit = 0;
cur_ccff_info->num_ccff = 0;
return;
}
void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info,
void update_ccff_info_num_mem_bit(t_ccff_info* cur_ccff_info,
int num_mem_bit) {
assert(NULL != cur_scff_info);
assert(NULL != cur_ccff_info);
cur_scff_info->num_mem_bit = num_mem_bit;
cur_ccff_info->num_mem_bit = num_mem_bit;
return;
}
@ -2573,8 +2573,8 @@ void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,
num_bl_per_sram, num_wl_per_sram);
break;
case SPICE_SRAM_SCAN_CHAIN:
cur_sram_orgz_info->scff_info = alloc_one_scff_info();
init_scff_info(cur_sram_orgz_info->scff_info, cur_mem_model);
cur_sram_orgz_info->ccff_info = alloc_one_ccff_info();
init_ccff_info(cur_sram_orgz_info->ccff_info, cur_mem_model);
break;
case SPICE_SRAM_STANDALONE:
cur_sram_orgz_info->standalone_sram_info = alloc_one_standalone_sram_info();
@ -2624,7 +2624,7 @@ void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,
free_one_mem_bank_info(cur_sram_orgz_info->mem_bank_info);
break;
case SPICE_SRAM_SCAN_CHAIN:
free_one_scff_info(cur_sram_orgz_info->scff_info);
free_one_ccff_info(cur_sram_orgz_info->ccff_info);
break;
case SPICE_SRAM_STANDALONE:
free_one_standalone_sram_info(cur_sram_orgz_info->standalone_sram_info);
@ -2831,7 +2831,7 @@ int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info) {
case SPICE_SRAM_STANDALONE:
return cur_sram_orgz_info->standalone_sram_info->num_mem_bit;
case SPICE_SRAM_SCAN_CHAIN:
return cur_sram_orgz_info->scff_info->num_mem_bit;
return cur_sram_orgz_info->ccff_info->num_mem_bit;
case SPICE_SRAM_MEMORY_BANK:
return cur_sram_orgz_info->mem_bank_info->num_mem_bit;
default:
@ -2854,7 +2854,7 @@ void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info,
update_standalone_sram_info_num_mem_bit(cur_sram_orgz_info->standalone_sram_info, new_num_mem_bit);
break;
case SPICE_SRAM_SCAN_CHAIN:
update_scff_info_num_mem_bit(cur_sram_orgz_info->scff_info, new_num_mem_bit);
update_ccff_info_num_mem_bit(cur_sram_orgz_info->ccff_info, new_num_mem_bit);
break;
case SPICE_SRAM_MEMORY_BANK:
update_mem_bank_info_num_mem_bit(cur_sram_orgz_info->mem_bank_info, new_num_mem_bit);
@ -2903,7 +2903,7 @@ void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info,
(*mem_model_ptr) = cur_sram_orgz_info->standalone_sram_info->mem_model;
break;
case SPICE_SRAM_SCAN_CHAIN:
(*mem_model_ptr) = cur_sram_orgz_info->scff_info->mem_model;
(*mem_model_ptr) = cur_sram_orgz_info->ccff_info->mem_model;
break;
case SPICE_SRAM_MEMORY_BANK:
(*mem_model_ptr) = cur_sram_orgz_info->mem_bank_info->mem_model;
@ -2929,7 +2929,7 @@ void update_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info,
cur_sram_orgz_info->standalone_sram_info->mem_model = cur_mem_model;
break;
case SPICE_SRAM_SCAN_CHAIN:
cur_sram_orgz_info->scff_info->mem_model = cur_mem_model;
cur_sram_orgz_info->ccff_info->mem_model = cur_mem_model;
break;
case SPICE_SRAM_MEMORY_BANK:
cur_sram_orgz_info->mem_bank_info->mem_model = cur_mem_model;

10
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h
View File

@ -235,7 +235,7 @@ void check_sram_spice_model_ports(t_spice_model* cur_spice_model,
boolean include_bl_wl);
void check_ff_spice_model_ports(t_spice_model* cur_spice_model,
boolean is_scff);
boolean is_ccff);
/* Functions to manipulate t_conf_bit and t_conf_bit_info */
void free_conf_bit(t_conf_bit* conf_bit);
@ -270,9 +270,9 @@ t_mem_bank_info* alloc_one_mem_bank_info();
void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info);
t_scff_info* alloc_one_scff_info();
t_ccff_info* alloc_one_ccff_info();
void free_one_scff_info(t_scff_info* scff_info);
void free_one_ccff_info(t_ccff_info* ccff_info);
t_standalone_sram_info* alloc_one_standalone_sram_info();
@ -299,10 +299,10 @@ void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,
void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info,
int num_mem_bit);
void init_scff_info(t_scff_info* cur_scff_info,
void init_ccff_info(t_ccff_info* cur_ccff_info,
t_spice_model* cur_mem_model);
void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info,
void update_ccff_info_num_mem_bit(t_ccff_info* cur_ccff_info,
int num_mem_bit);
void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info,

12
vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp
View File

@ -114,7 +114,7 @@ CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_nam
/************************************************************************
* Link circuit model to the SRAM organization
* Case 1: standalone organization required a SRAM circuit model
* Case 1: scan-chain organization required a SCFF circuit model
* Case 1: configuration-chain organization required a CCFF circuit model
* Case 1: memory-bank organization required a SRAM circuit model
***********************************************************************/
static
@ -128,9 +128,9 @@ void link_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz,
/* Check the type of SRAM_Ciruit_MODEL required by different sram organization */
/* check SRAM ports
* Checker for circuit models used by the SRAM organization
* either SRAMs or SCFFs
* 1. It will check the basic port required for SRAMs and SCFFs
* 2. It will check any special ports required for SRAMs and SCFFs
* either SRAMs or CCFFs
* 1. It will check the basic port required for SRAMs and CCFFs
* 2. It will check any special ports required for SRAMs and CCFFs
*/
switch (cur_sram_inf_orgz->type) {
case SPICE_SRAM_STANDALONE:
@ -145,8 +145,8 @@ void link_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz,
break;
case SPICE_SRAM_SCAN_CHAIN:
/* check Scan-chain Flip-flop ports */
cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_SCFF);
check_scff_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model);
cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_CCFF);
check_ccff_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model);
break;
case SPICE_SRAM_LOCAL_ENCODER:
/* Wipe out LOCAL ENCODER, it is not supported here ! */

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
View File

@ -157,7 +157,7 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
std::vector<e_spice_model_port_type> model_port_types;
/* Prepare a list of module port types to be added, the port type will be used to specify the port type in Verilog/SPICE module */
std::vector<ModuleManager::e_module_port_type> module_port_types;
/* Actual port size may be different from user specification. Think about SCFF */
/* Actual port size may be different from user specification. Think about CCFF */
size_t sram_port_size = port_size;
switch (sram_orgz_type) {
@ -172,7 +172,7 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT);
model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT);
module_port_types.push_back(ModuleManager::MODULE_OUTPUT_PORT);
/* SCFF head/tail are single-bit ports */
/* CCFF head/tail are single-bit ports */
sram_port_size = 1;
break;
case SPICE_SRAM_MEMORY_BANK: {

6
vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c
View File

@ -351,10 +351,10 @@ void fprint_spice_sram_one_outport(FILE* fp,
break;
case SPICE_SRAM_SCAN_CHAIN:
if (0 == port_type_index) {
port_name = "scff_out";
port_name = "ccff_out";
} else {
assert(1 == port_type_index);
port_name = "scff_outb";
port_name = "ccff_outb";
}
break;
case SPICE_SRAM_MEMORY_BANK:
@ -696,7 +696,7 @@ void fprint_global_pad_ports_spice_model(FILE* fp,
case SPICE_MODEL_LUT:
case SPICE_MODEL_FF:
case SPICE_MODEL_HARDLOGIC:
case SPICE_MODEL_SCFF:
case SPICE_MODEL_CCFF:
case SPICE_MODEL_INVBUF:
case SPICE_MODEL_PASSGATE:
case SPICE_MODEL_GATE:

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -79,7 +79,7 @@ char* generate_compact_verilog_grid_module_name(t_type_ptr phy_block_type,
/* ONLY for compact Verilog netlists:
* Update the grid_index_low and grid_index_high for each spice_models
* Currently, we focus on three spice_models: SRAMs/SCFFs/IOPADs
* Currently, we focus on three spice_models: SRAMs/CCFFs/IOPADs
*/
static
void compact_verilog_update_one_spice_model_grid_index(t_type_ptr phy_block_type,
@ -102,7 +102,7 @@ void compact_verilog_update_one_spice_model_grid_index(t_type_ptr phy_block_type
case SPICE_MODEL_HARDLOGIC:
case SPICE_MODEL_GATE:
break;
case SPICE_MODEL_SCFF:
case SPICE_MODEL_CCFF:
case SPICE_MODEL_SRAM:
stamped_cnt = spice_model[i].cnt;
spice_model[i].grid_index_low[grid_x][grid_y] = stamped_cnt;
@ -158,7 +158,7 @@ void compact_verilog_update_sram_orgz_info_grid_index(t_sram_orgz_info* cur_sram
/* ONLY for compact Verilog netlists:
* Update the grid_index_low and grid_index_high for each spice_models
* Currently, we focus on three spice_models: SRAMs/SCFFs/IOPADs
* Currently, we focus on three spice_models: SRAMs/CCFFs/IOPADs
* IMPORTANT: The sequence of for loop should be consistent with
* 1. bitstream logic block
* 2. verilog pbtypes logic block

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c
View File

@ -241,7 +241,7 @@ void dump_verilog_decoder(FILE* fp,
}
/* For standalone-SRAM configuration organization:
* Dump the module of configuration module which connect configuration ports to SRAMs/SCFFs
* Dump the module of configuration module which connect configuration ports to SRAMs/CCFFs
*/
static
void dump_verilog_standalone_sram_config_module(FILE* fp,
@ -288,7 +288,7 @@ void dump_verilog_standalone_sram_config_module(FILE* fp,
/* For scan-chain configuration organization:
* Dump the module of configuration module which connect configuration ports to SRAMs/SCFFs
* Dump the module of configuration module which connect configuration ports to SRAMs/CCFFs
*/
static
void dump_verilog_scan_chain_config_module(FILE* fp,
@ -331,7 +331,7 @@ void dump_verilog_scan_chain_config_module(FILE* fp,
fprintf(fp, ";\n");
/* Verilog Module body */
/* Connect the head of current scff to the tail of previous scff*/
/* Connect the head of current ccff to the tail of previous ccff*/
fprintf(fp, " ");
fprintf(fp, "assign ");
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 1, num_mem_bits - 1, -1, VERILOG_PORT_CONKT);
@ -405,7 +405,7 @@ void dump_verilog_membank_one_inv_module(FILE* fp,
}
/* For Memory-bank configuration organization:
* Dump the module of configuration module which connect configuration ports to SRAMs/SCFFs
* Dump the module of configuration module which connect configuration ports to SRAMs/CCFFs
*/
static
void dump_verilog_membank_config_module(FILE* fp,

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp
View File

@ -219,10 +219,10 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
/***************************************************************************************
* For scan-chain configuration organization:
* Generate the Verilog module of configuration module
* which connect configuration ports to SRAMs/SCFFs in a chain:
* which connect configuration ports to SRAMs/CCFFs in a chain:
*
* +------+ +------+ +------+
* sc_in--->| SCFF |--->| SCFF |---> ... --->| SCFF |----> sc_out
* sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out
* +------+ +------+ +------+
***************************************************************************************/
static
@ -264,7 +264,7 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager,
BasicPort sc_first_input_port(sc_input_port.get_name(), 1);
print_verilog_wire_connection(fp, sc_first_input_port, sc_head_port, false);
/* Connect the head of current scff to the tail of previous scff*/
/* Connect the head of current ccff to the tail of previous ccff*/
BasicPort chain_output_port(sc_input_port.get_name(), 1, num_mem_bits - 1);
BasicPort chain_input_port(sc_output_port.get_name(), 0, num_mem_bits - 2);
print_verilog_wire_connection(fp, chain_output_port, chain_input_port, false);
@ -281,11 +281,11 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager,
* Generate the configuration peripheral circuits for the top-level Verilog netlist
* This function will create Verilog modules depending on the configuration scheme:
* 1. Scan-chain:
* It will create a module which connects the Scan-Chain Flip-Flops (SCFFs)
* It will create a module which connects the Scan-Chain Flip-Flops (CCFFs)
* as a chain:
*
* +------+ +------+ +------+
* sc_in--->| SCFF |--->| SCFF |---> ... --->| SCFF |----> sc_out
* sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out
* +------+ +------+ +------+
*
* 2. Memory bank:

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -2041,7 +2041,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp,
/* Asserts*/
assert ((1 == num_sram_port) && (NULL != sram_port));
assert (NULL != sram_port[0]->spice_model);
assert ((SPICE_MODEL_SCFF == sram_port[0]->spice_model->type)
assert ((SPICE_MODEL_CCFF == sram_port[0]->spice_model->type)
|| (SPICE_MODEL_SRAM == sram_port[0]->spice_model->type));
/* Get the memory model */

36
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -191,8 +191,8 @@ void dump_verilog_top_netlist_scan_chain_ports(t_sram_orgz_info* cur_sram_orgz_i
static
void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
t_spice_model* scff_mem_model = NULL;
int num_scffs;
t_spice_model* ccff_mem_model = NULL;
int num_ccffs;
/* A valid file handler */
if (NULL == fp) {
@ -200,23 +200,23 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr
exit(1);
}
num_scffs = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
get_sram_orgz_info_mem_model(cur_sram_orgz_info, &scff_mem_model);
num_ccffs = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model);
/* Check */
assert( SPICE_MODEL_SCFF == scff_mem_model->type );
assert( SPICE_MODEL_CCFF == ccff_mem_model->type );
/* Delcare local wires */
fprintf(fp, " wire [0:%d] %s_scff_in_local_bus;\n",
num_scffs - 1, scff_mem_model->prefix);
fprintf(fp, " wire [0:%d] %s_ccff_in_local_bus;\n",
num_ccffs - 1, ccff_mem_model->prefix);
fprintf(fp, " wire [0:%d] %s_scff_out_local_bus;\n",
num_scffs - 1, scff_mem_model->prefix);
fprintf(fp, " wire [0:%d] %s_ccff_out_local_bus;\n",
num_ccffs - 1, ccff_mem_model->prefix);
/* Dump ports only visible during formal verification*/
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, " ");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0, num_scffs - 1,
0, num_ccffs - 1,
VERILOG_PORT_WIRE, false);
fprintf(fp, ";\n");
fprintf(fp, "`endif\n");
@ -224,8 +224,8 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr
/* Exception for head: connect to primary inputs */
/*
fprintf(fp, " assign %s_scff_in[%d] = %s;\n",
scff_mem_model->prefix, 0,
fprintf(fp, " assign %s_ccff_in[%d] = %s;\n",
ccff_mem_model->prefix, 0,
top_netlist_scan_chain_head_prefix);
*/
/* Connected the scan-chain flip-flops */
@ -234,10 +234,10 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr
fprintf(fp, " genvar i;\n");
fprintf(fp, " generate\n");
fprintf(fp, " for (i = %d; i < %d; i = i + 1) begin\n",
1, num_scffs - 1);
fprintf(fp, "assign %s_scff_in[i] = %s_scff_out[i - 1];\n",
scff_mem_model->prefix,
scff_mem_model->prefix);
1, num_ccffs - 1);
fprintf(fp, "assign %s_ccff_in[i] = %s_ccff_out[i - 1];\n",
ccff_mem_model->prefix,
ccff_mem_model->prefix);
fprintf(fp, " end\n");
fprintf(fp, " endgenerate;\n");
*/
@ -1102,7 +1102,7 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_in_local_bus (");
fprintf(fp, ".ccff_ccff_in_local_bus (");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, -1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
@ -1110,7 +1110,7 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_out_local_bus (");
fprintf(fp, ".ccff_ccff_out_local_bus (");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {

70
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -1214,12 +1214,12 @@ void dump_verilog_sram_one_local_outport(FILE* fp,
break;
case SPICE_SRAM_SCAN_CHAIN:
if (0 == port_type_index) {
port_name = "scff_out_local_bus";
port_name = "ccff_out_local_bus";
} else if (1 == port_type_index) {
port_name = "scff_outb_local_bus";
port_name = "ccff_outb_local_bus";
} else {
assert(-1 == port_type_index);
port_name = "scff_in_local_bus";
port_name = "ccff_in_local_bus";
}
break;
case SPICE_SRAM_MEMORY_BANK:
@ -1283,12 +1283,12 @@ void dump_verilog_sram_one_outport(FILE* fp,
break;
case SPICE_SRAM_SCAN_CHAIN:
if (0 == port_type_index) {
port_name = "scff_out";
port_name = "ccff_out";
} else if (1 == port_type_index) {
port_name = "scff_outb";
port_name = "ccff_outb";
} else {
assert(-1 == port_type_index);
port_name = "scff_in";
port_name = "ccff_in";
}
break;
case SPICE_SRAM_MEMORY_BANK:
@ -1380,7 +1380,7 @@ void dump_verilog_formal_verification_sram_ports(FILE* fp,
port_name = "out_fm";
break;
case SPICE_SRAM_SCAN_CHAIN:
mem_model = cur_sram_orgz_info->scff_info->mem_model;
mem_model = cur_sram_orgz_info->ccff_info->mem_model;
port_name = "out_fm";
break;
case SPICE_SRAM_MEMORY_BANK:
@ -1444,12 +1444,12 @@ void dump_verilog_sram_one_port(FILE* fp,
}
break;
case SPICE_SRAM_SCAN_CHAIN:
mem_model = cur_sram_orgz_info->scff_info->mem_model;
mem_model = cur_sram_orgz_info->ccff_info->mem_model;
if (0 == port_type_index) {
port_name = "scff_head";
port_name = "ccff_head";
} else if (1 == port_type_index) {
assert(1 == port_type_index);
port_name = "scff_tail";
port_name = "ccff_tail";
/* Special case: scan-chain ff output should be an output always */
if (VERILOG_PORT_INPUT == dump_port_type) {
actual_dump_port_type = VERILOG_PORT_OUTPUT;
@ -1588,7 +1588,7 @@ void dump_verilog_sram_local_ports(FILE* fp,
case SPICE_SRAM_SCAN_CHAIN:
/* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_head(");
fprintf(fp, ".ccff_ccff_head(");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_lsb, sram_lsb,
@ -1599,7 +1599,7 @@ void dump_verilog_sram_local_ports(FILE* fp,
fprintf(fp, ",\n");
/* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_tail(");
fprintf(fp, ".ccff_ccff_tail(");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_msb, sram_msb,
@ -1827,7 +1827,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i
assert(NULL != cur_sram_orgz_info);
assert(NULL != cur_sram_verilog_model);
assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type)
|| (SPICE_MODEL_SCFF == cur_sram_verilog_model->type));
|| (SPICE_MODEL_CCFF == cur_sram_verilog_model->type));
/* Get current index of SRAM module */
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
@ -1993,7 +1993,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
assert(NULL != cur_sram_orgz_info);
assert(NULL != cur_sram_verilog_model);
assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type)
|| (SPICE_MODEL_SCFF == cur_sram_verilog_model->type));
|| (SPICE_MODEL_CCFF == cur_sram_verilog_model->type));
/* Get current index of SRAM module */
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
@ -2119,7 +2119,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
return;
}
void dump_verilog_scff_config_bus(FILE* fp,
void dump_verilog_ccff_config_bus(FILE* fp,
t_spice_model* mem_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int lsb, int msb,
@ -2128,7 +2128,7 @@ void dump_verilog_scff_config_bus(FILE* fp,
/* Check */
assert(NULL != mem_spice_model);
assert(SPICE_MODEL_SCFF == mem_spice_model->type);
assert(SPICE_MODEL_CCFF == mem_spice_model->type);
/* Check the file handler*/
if (NULL == fp) {
@ -2172,17 +2172,17 @@ void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model,
/* Check */
assert(NULL != mem_spice_model);
assert((SPICE_MODEL_SRAM == mem_spice_model->type)
|| (SPICE_MODEL_SCFF == mem_spice_model->type));
|| (SPICE_MODEL_CCFF == mem_spice_model->type));
/* Depend on the style of configuraion circuit */
switch (cur_sram_orgz_info->type) {
case SPICE_SRAM_STANDALONE:
break;
case SPICE_SRAM_SCAN_CHAIN:
/* We need to connect SCFF inputs and outputs in cacading
/* We need to connect CCFF inputs and outputs in cacading
* Scan-chain FF outputs are directly wired to SRAM inputs of MUXes
*/
/* Connect first SCFF to the head */
/* Connect first CCFF to the head */
/*
fprintf(fp, "assign ");
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram, -1, VERILOG_PORT_CONKT);
@ -2190,7 +2190,7 @@ void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model,
dump_verilog_sram_one_port(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram, 0, VERILOG_PORT_CONKT);
fprintf(fp, ";\n");
*/
/* Connect last SCFF to the tail */
/* Connect last CCFF to the tail */
/*
fprintf(fp, "assign ");
dump_verilog_sram_one_port(fp, cur_sram_orgz_info, cur_num_sram + num_mem_conf_bits - 1, cur_num_sram + num_mem_conf_bits - 1, 1, VERILOG_PORT_CONKT);
@ -2198,8 +2198,8 @@ void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model,
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_mem_conf_bits - 1, cur_num_sram + num_mem_conf_bits - 1, 0, VERILOG_PORT_CONKT);
fprintf(fp, ";\n");
*/
/* Connect SCFFs into chains */
/* Cascade the SCFF between head and tail */
/* Connect CCFFs into chains */
/* Cascade the CCFF between head and tail */
/*
if (1 < num_mem_conf_bits) {
fprintf(fp, "assign ");
@ -2359,10 +2359,10 @@ void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
1, VERILOG_PORT_WIRE);
fprintf(fp, ";\n");
/* We need to connect SCFF inputs and outputs in cacading
/* We need to connect CCFF inputs and outputs in cacading
* Scan-chain FF outputs are directly wired to SRAM inputs of MUXes
*/
/* Connect first SCFF to the head */
/* Connect first CCFF to the head */
fprintf(fp, "assign ");
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
@ -2373,7 +2373,7 @@ void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
cur_num_sram, cur_num_sram,
-1, VERILOG_PORT_CONKT);
fprintf(fp, ";\n");
/* Connect last SCFF to the tail */
/* Connect last CCFF to the tail */
fprintf(fp, "assign ");
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_mux_conf_bits - 1, cur_num_sram + num_mux_conf_bits - 1,
@ -2384,10 +2384,10 @@ void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
cur_num_sram + num_mux_conf_bits - 1, cur_num_sram + num_mux_conf_bits - 1,
0, VERILOG_PORT_CONKT);
fprintf(fp, ";\n");
/* Connect SCFFs into chains */
/* Connect the first SCFF (LSB) to the head */
/* Connect the last SCFF (MSB) to the tail */
/* Cascade the SCFF between head and tail */
/* Connect CCFFs into chains */
/* Connect the first CCFF (LSB) to the head */
/* Connect the last CCFF (MSB) to the tail */
/* Cascade the CCFF between head and tail */
if (1 < num_mux_conf_bits) {
fprintf(fp, "assign ");
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
@ -2784,20 +2784,20 @@ void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur
fprintf(fp, ";\n");
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_WIRE);
fprintf(fp, ";\n");
/* Connect first SCFF to the head */
/* Connect first CCFF to the head */
fprintf(fp, "assign ");
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, lsb, -1, VERILOG_PORT_CONKT);
fprintf(fp, " = ");
dump_verilog_sram_one_port(fp, cur_sram_orgz_info, lsb, lsb, 0, VERILOG_PORT_CONKT);
fprintf(fp, ";\n");
/* Connect last SCFF to the tail */
/* Connect last CCFF to the tail */
fprintf(fp, "assign ");
dump_verilog_sram_one_port(fp, cur_sram_orgz_info, msb, msb, 1, VERILOG_PORT_CONKT);
fprintf(fp, " = ");
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, msb, msb, 0, VERILOG_PORT_CONKT);
fprintf(fp, ";\n");
/* Connect SCFFs into chains */
/* Cascade the SCFF between head and tail */
/* Connect CCFFs into chains */
/* Cascade the CCFF between head and tail */
if (1 < msb - lsb) {
fprintf(fp, "assign ");
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
@ -3042,7 +3042,7 @@ int dump_verilog_mem_module_one_port_map(FILE* fp,
/*
* Dump the port map of a memory module
* which consist of a number of SRAMs/SCFFs etc.
* which consist of a number of SRAMs/CCFFs etc.
*/
void dump_verilog_mem_module_port_map(FILE* fp,
t_spice_model* mem_model,
@ -3152,7 +3152,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
assert(NULL != cur_sram_orgz_info);
assert(NULL != cur_sram_verilog_model);
assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type)
|| (SPICE_MODEL_SCFF == cur_sram_verilog_model->type));
|| (SPICE_MODEL_CCFF == cur_sram_verilog_model->type));
switch (cur_sram_orgz_info->type) {
case SPICE_SRAM_MEMORY_BANK:

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -164,7 +164,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i
void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* sram_verilog_model);
void dump_verilog_scff_config_bus(FILE* fp,
void dump_verilog_ccff_config_bus(FILE* fp,
t_spice_model* mem_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int lsb, int msb,