implementing mux Verilog generation. Bugs detected, fixing ongoing
This commit is contained in:
tangxifan
parent
fde9c8b4ec
commit
e623c19055
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@ -298,6 +298,22 @@ size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const {
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return buffer_num_levels_[model_id];
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}
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/* Return the location map of intermediate buffers
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* that are inserted inside LUT multiplexing structures
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*/
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std::string CircuitLibrary::lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const {
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/* validate the model_id */
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VTR_ASSERT(valid_model_id(model_id));
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/* validate the circuit model type is BUF */
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VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id));
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/* if we have an intermediate buffer, we return something, otherwise return an empty map */
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if (true == is_lut_intermediate_buffered(model_id)) {
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return buffer_location_maps_[model_id][LUT_INTER_BUFFER];
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} else {
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return std::string();
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}
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}
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/* Return the number of levels of delay types for a circuit model */
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size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const {
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/* validate the model_id */
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@ -239,6 +239,7 @@ class CircuitLibrary {
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/* Buffer information */
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enum e_spice_model_buffer_type buffer_type(const CircuitModelId& model_id) const;
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size_t buffer_num_levels(const CircuitModelId& model_id) const;
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std::string lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const;
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/* Delay information */
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size_t num_delay_info(const CircuitModelId& model_id) const;
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public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/
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@ -43,6 +43,20 @@ MuxGraph::node_range MuxGraph::nodes() const {
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return vtr::make_range(node_ids_.begin(), node_ids_.end());
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}
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/* Find the non-input nodes */
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std::vector<MuxNodeId> MuxGraph::non_input_nodes() const {
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std::vector<MuxNodeId> node_list;
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for (const auto& node : nodes()) {
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/* Bypass any nodes which are not OUTPUT and INTERNAL */
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if (MUX_INPUT_NODE == node_types_[node]) {
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continue;
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}
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/* Reach here, this is either an OUTPUT or INTERNAL node */
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node_list.push_back(node);
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}
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return node_list;
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}
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MuxGraph::edge_range MuxGraph::edges() const {
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return vtr::make_range(edge_ids_.begin(), edge_ids_.end());
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}
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@ -137,6 +151,47 @@ size_t MuxGraph::num_memory_bits() const {
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return mem_ids_.size();
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}
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/* Find the number of nodes at a given level in the MUX graph */
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size_t MuxGraph::num_nodes_at_level(const size_t& level) const {
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/* validate the level numbers */
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VTR_ASSERT_SAFE(valid_level(level));
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VTR_ASSERT_SAFE(valid_mux_graph());
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size_t num_nodes = 0;
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for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) {
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num_nodes += node_lookup_[level][node_type].size();
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}
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return num_nodes;
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}
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/* Find the level of a node */
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size_t MuxGraph::node_level(const MuxNodeId& node) const {
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/* validate the node */
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VTR_ASSERT(valid_node_id(node));
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return node_levels_[node];
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}
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/* Find the index of a node at its level */
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size_t MuxGraph::node_index_at_level(const MuxNodeId& node) const {
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/* validate the node */
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VTR_ASSERT(valid_node_id(node));
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return node_ids_at_level_[node];
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}
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/* Find the input edges for a node */
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std::vector<MuxEdgeId> MuxGraph::node_in_edges(const MuxNodeId& node) const {
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/* validate the node */
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VTR_ASSERT(valid_node_id(node));
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return node_in_edges_[node];
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}
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/* Find the input nodes for a edge */
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std::vector<MuxNodeId> MuxGraph::edge_src_nodes(const MuxEdgeId& edge) const {
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/* validate the edge */
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VTR_ASSERT(valid_edge_id(edge));
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return edge_src_nodes_[edge];
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}
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/* Find the mem that control the edge */
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MuxMemId MuxGraph::find_edge_mem(const MuxEdgeId& edge) const {
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/* validate the edge */
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@ -846,6 +901,10 @@ bool MuxGraph::valid_output_id(const MuxOutputId& output_id) const {
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return true;
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}
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bool MuxGraph::valid_level(const size_t& level) const {
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return level < num_levels();
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}
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bool MuxGraph::valid_node_lookup() const {
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return node_lookup_.empty();
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}
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@ -58,6 +58,8 @@ class MuxGraph {
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MuxGraph();
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public: /* Public accessors: Aggregates */
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node_range nodes() const;
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/* Find the non-input nodes */
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std::vector<MuxNodeId> non_input_nodes() const;
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edge_range edges() const;
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mem_range memories() const;
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public: /* Public accessors: Data query */
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@ -73,6 +75,16 @@ class MuxGraph {
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size_t num_levels() const;
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/* Find the number of SRAMs in the MUX graph */
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size_t num_memory_bits() const;
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/* Find the number of nodes at a given level in the MUX graph */
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size_t num_nodes_at_level(const size_t& level) const;
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/* Find the level of a node */
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size_t node_level(const MuxNodeId& node) const;
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/* Find the index of a node at its level */
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size_t node_index_at_level(const MuxNodeId& node) const;
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/* Find the input edges for a node */
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std::vector<MuxEdgeId> node_in_edges(const MuxNodeId& node) const;
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/* Find the input nodes for a edge */
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std::vector<MuxNodeId> edge_src_nodes(const MuxEdgeId& edge) const;
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/* Find the mem that control the edge */
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MuxMemId find_edge_mem(const MuxEdgeId& edge) const;
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/* Identify if the edge is controlled by the inverted output of a mem */
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@ -122,6 +134,7 @@ class MuxGraph {
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bool valid_mem_id(const MuxMemId& mem) const;
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bool valid_input_id(const MuxInputId& input_id) const;
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bool valid_output_id(const MuxOutputId& output_id) const;
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bool valid_level(const size_t& level) const;
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/* validate/invalidate node lookup */
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bool valid_node_lookup() const;
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void invalidate_node_lookup();
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@ -150,6 +150,34 @@ size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size,
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return num_input_per_unit;
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}
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/**************************************************
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* Find if there is an intermediate buffer
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* locating at the multiplexing structure of a LUT
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*************************************************/
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bool require_intermediate_buffer_at_mux_level(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const size_t& node_level) {
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std::string intermediate_buffer_location_map;
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/* ONLY for LUTs: intermediate buffers may exist if specified */
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if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
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intermediate_buffer_location_map = circuit_lib.lut_intermediate_buffer_location_map(circuit_model);
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}
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/* If no location map is specified, we can return here */
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if (intermediate_buffer_location_map.empty()) {
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return false;
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}
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/* We have a location map. Make sure we are in the range */
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if (node_level >= intermediate_buffer_location_map.length()) {
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return false;
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}
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/* '1' indicates that the location is needed */
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if ('1' == intermediate_buffer_location_map[node_level]) {
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return true;
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}
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return false;
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}
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/**************************************************
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* Convert a linked list of MUX architecture to MuxLibrary
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* TODO: this function will be deleted when MUXLibrary fully
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@ -29,6 +29,10 @@ size_t find_treelike_mux_num_levels(const size_t& mux_size);
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size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size,
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const size_t& mux_level);
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bool require_intermediate_buffer_at_mux_level(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const size_t& node_level);
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MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head);
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#endif
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@ -7,6 +7,27 @@
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#include "fpga_x2p_naming.h"
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/************************************************
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* Generate the node name for a multiplexing structure
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* Case 1 : If there is an intermediate buffer followed by,
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* the node name will be mux_l<node_level>_in_buf
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* Case 1 : If there is NO intermediate buffer followed by,
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* the node name will be mux_l<node_level>_in
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***********************************************/
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std::string generate_verilog_mux_node_name(const size_t& node_level,
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const bool& add_buffer_postfix) {
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/* Generate the basic node_name */
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std::string node_name = "mux_l" + std::to_string(node_level) + "_in";
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/* Add a postfix upon requests */
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if (true == add_buffer_postfix) {
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/* '1' indicates that the location is needed */
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node_name += "_buf";
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}
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return node_name;
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}
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/************************************************
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* Generate the module name for a multiplexer in Verilog format
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* Different circuit model requires different names:
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@ -11,6 +11,9 @@
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#include "circuit_library.h"
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std::string generate_verilog_mux_node_name(const size_t& node_level,
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const bool& add_buffer_postfix);
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std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const size_t& mux_size,
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@ -50,6 +50,29 @@ std::vector<BasicPort> ModuleManager::module_ports_by_type(const ModuleId& modul
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return ports;
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}
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/* Find a port of a module by a given name */
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ModulePortId ModuleManager::find_module_port(const ModuleId& module_id, const std::string& port_name) const {
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/* Validate the module id */
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VTR_ASSERT(valid_module_id(module_id));
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/* Iterate over the ports of the module */
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for (const auto& port : port_ids_[module_id]) {
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if (0 == port_name.compare(ports_[module_id][port].get_name())) {
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/* Find it, return the id */
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return port;
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}
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}
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/* Not found, return an invalid id */
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return ModulePortId::INVALID();
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}
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/* Find the Port information with a given port id */
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BasicPort ModuleManager::module_port(const ModuleId& module_id, const ModulePortId& port_id) const {
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/* Validate the module and port id */
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VTR_ASSERT(valid_module_port_id(module_id, port_id));
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return ports_[module_id][port_id];
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}
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/* Find the module id by a given name, return invalid if not found */
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ModuleId ModuleManager::find_module(const std::string& name) const {
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if (name_id_map_.find(name) != name_id_map_.end()) {
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@ -37,6 +37,11 @@ class ModuleManager {
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std::string module_name(const ModuleId& module_id) const;
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std::string module_port_type_str(const enum e_module_port_type& port_type) const;
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std::vector<BasicPort> module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const;
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/* Find a port of a module by a given name */
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ModulePortId find_module_port(const ModuleId& module_id, const std::string& port_name) const;
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/* Find the Port information with a given port id */
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BasicPort module_port(const ModuleId& module_id, const ModulePortId& port_id) const;
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/* Find a module by a given name */
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ModuleId find_module(const std::string& name) const;
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/* Find the number of instances of a child module in the parent module */
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size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const;
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@ -6,6 +6,7 @@
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* and the full multiplexer
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**********************************************/
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#include <string>
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#include <algorithm>
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#include "util.h"
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#include "vtr_assert.h"
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@ -74,7 +75,7 @@ void generate_verilog_cmos_mux_branch_body_structural(ModuleManager& module_mana
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if (0 == edges.size()) {
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continue;
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}
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/* TODO: Output a tgate use a module manager */
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/* Output a tgate use a module manager */
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/* Create a port-to-port name map */
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std::map<std::string, BasicPort> port2port_name_map;
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/* input port */
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@ -693,6 +694,213 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager,
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}
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}
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/********************************************************************
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* Generate the internal logic (multiplexing structure) for
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* a multiplexer or LUT in Verilog codes
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* This function will :
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* 1. build a multiplexing structure by instanciating the branch circuits
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* generated before or standard cells MUX2
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* 2. add intermediate buffers between multiplexing stages if specified.
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*******************************************************************/
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static
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void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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std::fstream& fp,
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const ModuleId& module_id,
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const CircuitModelId& circuit_model,
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const MuxGraph& mux_graph) {
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/* Make sure we have a valid file handler*/
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check_file_handler(fp);
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/* Find the actual mux size */
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size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs());
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/* TODO: these are duplicated codes, find a way to simplify it!!!
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* Get the regular (non-mode-select) sram ports from the mux
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*/
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std::vector<CircuitPortId> mux_regular_sram_ports;
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for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true)) {
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/* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules
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* Here we just bypass it.
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*/
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if (true == circuit_lib.port_is_mode_select(port)) {
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continue;
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}
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mux_regular_sram_ports.push_back(port);
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}
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VTR_ASSERT(1 == mux_regular_sram_ports.size());
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print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a CMOS MUX module -----"));
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/* Print local wires which are the nodes in the mux graph */
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for (size_t level = 0; level < mux_graph.num_levels(); ++level) {
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/* Print the internal wires located at this level */
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BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level));
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fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl;
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/* Identify if an intermediate buffer is needed */
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if (false == require_intermediate_buffer_at_mux_level(circuit_lib, circuit_model, level)) {
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continue;
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}
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BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level));
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fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl;
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}
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print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----"));
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX modules -----"));
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/* Iterate over all the internal nodes and output nodes in the mux graph */
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for (const auto& node : mux_graph.non_input_nodes()) {
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/* Get the size of branch circuit
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* Instanciate an branch circuit by the size (fan-in) of the node
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*/
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size_t branch_size = mux_graph.node_in_edges(node).size();
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/* Instanciate the branch module:
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* Case 1: the branch module is a standard cell MUX2
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* Case 2: the branch module is a tgate-based module
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*/
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std::string branch_module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix);
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/* Get the moduleId for the submodule */
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ModuleId branch_module_id = module_manager.find_module(branch_module_name);
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/* We must have one */
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VTR_ASSERT(ModuleId::INVALID() != branch_module_id);
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/* Get the node level and index in the current level */
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size_t output_node_level = mux_graph.node_level(node);
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size_t output_node_index_at_level = mux_graph.node_index_at_level(node);
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/* Get the nodes which drive the root_node */
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std::vector<MuxNodeId> input_nodes;
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for (const auto& edge : mux_graph.node_in_edges(node)) {
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/* Get the nodes drive the edge */
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for (const auto& src_node : mux_graph.edge_src_nodes(edge)) {
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input_nodes.push_back(src_node);
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}
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}
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/* Number of inputs should match the branch_input_size!!! */
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VTR_ASSERT(input_nodes.size() == branch_size);
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/* Get the mems in the branch circuits */
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std::vector<MuxMemId> mems;
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for (const auto& edge : mux_graph.node_in_edges(node)) {
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/* Get the mem control the edge */
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MuxMemId mem = mux_graph.find_edge_mem(edge);
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/* Add the mem if it is not in the list */
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if (mems.end() == std::find(mems.begin(), mems.end(), mem)) {
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mems.push_back(mem);
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}
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}
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/* Create a port-to-port map */
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std::map<std::string, BasicPort> port2port_name_map;
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/* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */
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/* TODO: for clean representation, need to merge the node names in [a:b] format, if possible!!!
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* All the input node names organized in bus
|
||||
*/
|
||||
std::vector<BasicPort> branch_node_input_ports;
|
||||
for (const auto& input_node : input_nodes) {
|
||||
/* Generate the port info of each input node */
|
||||
size_t input_node_level = mux_graph.node_level(input_node);
|
||||
size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node);
|
||||
BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, require_intermediate_buffer_at_mux_level(circuit_lib, circuit_model, input_node_level)), input_node_index_at_level, input_node_index_at_level);
|
||||
branch_node_input_ports.push_back(branch_node_input_port);
|
||||
}
|
||||
/* Try to combine the ports */
|
||||
std::vector<BasicPort> combined_branch_node_input_ports = combine_verilog_ports(branch_node_input_ports);
|
||||
/* If we have more than 1 port in the combined ports ,
|
||||
*
|
||||
* output a local wire */
|
||||
VTR_ASSERT(0 < combined_branch_node_input_ports.size());
|
||||
/* Create the port info for the input */
|
||||
BasicPort instance_input_port;
|
||||
if (1 == combined_branch_node_input_ports.size()) {
|
||||
instance_input_port = combined_branch_node_input_ports[0];
|
||||
} else {
|
||||
/* TODO: the naming could be more flexible? */
|
||||
instance_input_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_in");
|
||||
/* Deposite a [0:0] port */
|
||||
instance_input_port.set_width(1);
|
||||
for (const auto& port : combined_branch_node_input_ports) {
|
||||
instance_input_port.combine(port);
|
||||
}
|
||||
/* Print a local wire for the merged ports */
|
||||
fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_input_port);
|
||||
fp << " = " << generate_verilog_ports(combined_branch_node_input_ports);
|
||||
fp << ";" << std::endl;
|
||||
}
|
||||
|
||||
/* Link nodes to input ports for the branch module */
|
||||
/* TODO: the naming could be more flexible? */
|
||||
ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in");
|
||||
VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id);
|
||||
/* Get the port from module */
|
||||
BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id);
|
||||
/* Double check: Port width should match the number of input nodes */
|
||||
VTR_ASSERT(module_input_port.get_width() == instance_input_port.get_width());
|
||||
port2port_name_map[module_input_port.get_name()] = instance_input_port;
|
||||
|
||||
/* Link nodes to output ports for the branch module */
|
||||
BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level);
|
||||
ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out");
|
||||
VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id);
|
||||
/* Get the port from module */
|
||||
BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id);
|
||||
/* Double check: Port width should match the number of output nodes */
|
||||
VTR_ASSERT(module_output_port.get_width() == instance_output_port.get_width());
|
||||
port2port_name_map[module_output_port.get_name()] = module_output_port;
|
||||
|
||||
/* All the mem node names organized in bus */
|
||||
std::vector<BasicPort> branch_node_mem_ports;
|
||||
for (const auto& mem : mems) {
|
||||
/* Generate the port info of each mem node */
|
||||
BasicPort branch_node_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem));
|
||||
branch_node_mem_ports.push_back(branch_node_mem_port);
|
||||
}
|
||||
/* Try to combine the ports */
|
||||
std::vector<BasicPort> combined_branch_node_mem_ports = combine_verilog_ports(branch_node_mem_ports);
|
||||
/* If we have more than 1 port in the combined ports ,
|
||||
*
|
||||
* output a local wire */
|
||||
VTR_ASSERT(0 < combined_branch_node_mem_ports.size());
|
||||
/* Create the port info for the input */
|
||||
BasicPort instance_mem_port;
|
||||
if (1 == combined_branch_node_mem_ports.size()) {
|
||||
instance_mem_port = combined_branch_node_mem_ports[0];
|
||||
} else {
|
||||
/* TODO: the naming could be more flexible? */
|
||||
instance_mem_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_mem");
|
||||
/* Deposite a [0:0] port */
|
||||
instance_mem_port.set_width(1);
|
||||
/* TODO: combine the ports could be a function? */
|
||||
for (const auto& port : combined_branch_node_mem_ports) {
|
||||
instance_mem_port.combine(port);
|
||||
}
|
||||
/* Print a local wire for the merged ports */
|
||||
fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_mem_port);
|
||||
fp << " = " << generate_verilog_ports(combined_branch_node_mem_ports);
|
||||
fp << ";" << std::endl;
|
||||
}
|
||||
|
||||
/* Link nodes to input ports for the branch module */
|
||||
/* TODO: the naming could be more flexible? */
|
||||
ModulePortId module_mem_port_id = module_manager.find_module_port(branch_module_id, "mem");
|
||||
VTR_ASSERT(ModulePortId::INVALID() != module_mem_port_id);
|
||||
/* Get the port from module */
|
||||
BasicPort module_mem_port = module_manager.module_port(branch_module_id, module_mem_port_id);
|
||||
/* Double check: Port width should match the number of input nodes */
|
||||
VTR_ASSERT(module_mem_port.get_width() == instance_mem_port.get_width());
|
||||
port2port_name_map[module_mem_port.get_name()] = instance_mem_port;
|
||||
|
||||
/* Output an instance of the module */
|
||||
print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model));
|
||||
/* IMPORTANT: this update MUST be called after the instance outputting!!!!
|
||||
* update the module manager with the relationship between the parent and child modules
|
||||
*/
|
||||
module_manager.add_child_module(module_id, branch_module_id);
|
||||
|
||||
/* TODO: Now we need to add intermediate buffers by instanciating the modules */
|
||||
}
|
||||
print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX modules -----"));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* Generate Verilog codes modeling a CMOS multiplexer with the given size
|
||||
* The Verilog module will consist of three parts:
|
||||
|
|
@ -731,7 +939,6 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager,
|
|||
/* Check codes to ensure the port of Verilog netlists will match */
|
||||
/* MUX graph must have only 1 output */
|
||||
VTR_ASSERT(1 == mux_input_ports.size());
|
||||
VTR_ASSERT(1 == mux_input_ports.size());
|
||||
/* A quick check on the model ports */
|
||||
if ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model))
|
||||
|| ((SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model))
|
||||
|
|
@ -802,6 +1009,7 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager,
|
|||
|
||||
/* TODO: Print the internal logic in Verilog codes */
|
||||
/* TODO: Print the Multiplexing structure in Verilog codes */
|
||||
generate_verilog_cmos_mux_module_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
|
||||
/* TODO: Print the input buffers in Verilog codes */
|
||||
/* TODO: Print the output buffers in Verilog codes */
|
||||
|
||||
|
|
|
|||
|
|
@ -128,6 +128,25 @@ void print_verilog_module_declaration(std::fstream& fp,
|
|||
|
||||
/************************************************
|
||||
* Print an instance for a Verilog module
|
||||
* This function will output the port map
|
||||
* by referring to a port-to-port mapping:
|
||||
* <module_port_name> -> <instance_port_name>
|
||||
* The key of the port-to-port mapping is the
|
||||
* port name of the module:
|
||||
* The value of the port-to-port mapping is the
|
||||
* port information of the instance
|
||||
* With link between module and instance, the function
|
||||
* can output a Verilog instance easily, supporting
|
||||
* both explicit port mapping:
|
||||
* .<module_port_name>(<instance_port_name>)
|
||||
* and inexplicit port mapping
|
||||
* <instance_port_name>
|
||||
*
|
||||
* Note that, it is not necessary that
|
||||
* the port-to-port mapping covers all the module ports.
|
||||
* Any instance/module port which are not specified in the
|
||||
* port-to-port mapping will be output by the module
|
||||
* port name.
|
||||
***********************************************/
|
||||
void print_verilog_module_instance(std::fstream& fp,
|
||||
const ModuleManager& module_manager,
|
||||
|
|
@ -168,6 +187,11 @@ void print_verilog_module_instance(std::fstream& fp,
|
|||
/* Try to find the instanced port name in the name map */
|
||||
if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) {
|
||||
/* Found it, we assign the port name */
|
||||
/* TODO: make sure the port width matches! */
|
||||
ModulePortId module_port_id = module_manager.find_module_port(child_module_id, port.get_name());
|
||||
/* Get the port from module */
|
||||
BasicPort module_port = module_manager.module_port(child_module_id, module_port_id);
|
||||
VTR_ASSERT(module_port.get_width() == port2port_name_map.at(port.get_name()).get_width());
|
||||
fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name()));
|
||||
} else {
|
||||
/* Not found, we give the default port name */
|
||||
|
|
@ -197,7 +221,9 @@ void print_verilog_module_end(std::fstream& fp,
|
|||
fp << std::endl;
|
||||
}
|
||||
|
||||
/* Generate a string of a Verilog port */
|
||||
/************************************************
|
||||
* Generate a string of a Verilog port
|
||||
***********************************************/
|
||||
std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_port_type,
|
||||
const BasicPort& port_info) {
|
||||
std::string verilog_line;
|
||||
|
|
@ -224,4 +250,86 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p
|
|||
return verilog_line;
|
||||
}
|
||||
|
||||
/************************************************
|
||||
* This function takes a list of ports and
|
||||
* combine the port string by comparing the name
|
||||
* and width of ports.
|
||||
* For example, two ports A and B share the same name is
|
||||
* mergable as long as A's MSB + 1 == B's LSB
|
||||
* Note that the port sequence really matters!
|
||||
* This function will NOT change the sequence
|
||||
* of ports in the list port_info
|
||||
***********************************************/
|
||||
std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports) {
|
||||
std::vector<BasicPort> merged_ports;
|
||||
|
||||
/* Directly return if there are no ports */
|
||||
if (0 == ports.size()) {
|
||||
return merged_ports;
|
||||
}
|
||||
/* Push the first port to the merged ports */
|
||||
merged_ports.push_back(ports[0]);
|
||||
|
||||
/* Iterate over ports */
|
||||
for (const auto& port : ports) {
|
||||
/* Bypass the first port, it is already in the list */
|
||||
if (&port == &ports[0]) {
|
||||
continue;
|
||||
}
|
||||
/* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */
|
||||
for (auto& merged_port : merged_ports) {
|
||||
if (0 != port.get_name().compare(merged_port.get_name())) {
|
||||
/* Unable to merge, add the port to merged port list */
|
||||
merged_ports.push_back(port);
|
||||
/* Go to next */
|
||||
break;
|
||||
}
|
||||
/* May be merged, check LSB of port and MSB of merged_port */
|
||||
if (merged_port.get_msb() + 1 != port.get_lsb()) {
|
||||
/* Unable to merge, add the port to merged port list */
|
||||
merged_ports.push_back(port);
|
||||
/* Go to next */
|
||||
break;
|
||||
}
|
||||
/* Reach here, we should merge the ports,
|
||||
* LSB of merged_port remains the same,
|
||||
* MSB of merged_port will be updated
|
||||
* to the MSB of port
|
||||
*/
|
||||
merged_port.set_msb(port.get_msb());
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return merged_ports;
|
||||
}
|
||||
|
||||
/************************************************
|
||||
* Generate the string of a list of verilog ports
|
||||
***********************************************/
|
||||
std::string generate_verilog_ports(const std::vector<BasicPort>& merged_ports) {
|
||||
|
||||
/* Output the string of ports:
|
||||
* If there is only one port in the merged_port list
|
||||
* we only output the port.
|
||||
* If there are more than one port in the merged port list, we output an concatenated port:
|
||||
* {<port1>, <port2>, ... <last_port>}
|
||||
*/
|
||||
VTR_ASSERT(0 < merged_ports.size());
|
||||
if ( 1 == merged_ports.size()) {
|
||||
/* Use connection type of verilog port */
|
||||
return generate_verilog_port(VERILOG_PORT_CONKT, merged_ports[0]);
|
||||
}
|
||||
|
||||
std::string verilog_line = "{";
|
||||
for (const auto& port : merged_ports) {
|
||||
/* The first port does not need a comma */
|
||||
if (&port != &merged_ports[0]) {
|
||||
verilog_line += ", ";
|
||||
}
|
||||
verilog_line += generate_verilog_port(VERILOG_PORT_CONKT, merged_ports[0]);
|
||||
}
|
||||
verilog_line += "}";
|
||||
|
||||
return verilog_line;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -40,4 +40,8 @@ void print_verilog_module_end(std::fstream& fp,
|
|||
std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type,
|
||||
const BasicPort& port_info);
|
||||
|
||||
std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports);
|
||||
|
||||
std::string generate_verilog_ports(const std::vector<BasicPort>& merged_ports);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue