Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring

vpr7_x2p/vpr/SRC/device/mux_graph.cpp

@@ -67,6 +67,18 @@ size_t MuxGraph::num_inputs() const {
   return num_inputs;
 }
 
+/* Return the node ids of all the inputs of the multiplexer */
+std::vector<MuxNodeId> MuxGraph::inputs() const {
+  std::vector<MuxNodeId> input_nodes; 
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  /* Add the input nodes in each level */
+  for (auto node_per_level : node_lookup_) {
+    input_nodes.insert(input_nodes.end(), node_per_level[MUX_INPUT_NODE].begin(), node_per_level[MUX_INPUT_NODE].end());
+  }
+  return input_nodes;
+}
+
 /* Find the number of outputs in the MUX graph */
 size_t MuxGraph::num_outputs() const {
   /* need to check if the graph is valid or not */
@@ -79,6 +91,36 @@ size_t MuxGraph::num_outputs() const {
   return num_outputs;
 }
 
+/* Return the node ids of all the outputs of the multiplexer */
+std::vector<MuxNodeId> MuxGraph::outputs() const {
+  std::vector<MuxNodeId> output_nodes; 
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  /* Add the output nodes in each level */
+  for (auto node_per_level : node_lookup_) {
+    output_nodes.insert(output_nodes.end(), node_per_level[MUX_OUTPUT_NODE].begin(), node_per_level[MUX_OUTPUT_NODE].end());
+  }
+  return output_nodes;
+}
+
+/* Find the edge between two MUX nodes */
+std::vector<MuxEdgeId> MuxGraph::find_edges(const MuxNodeId& from_node, const MuxNodeId& to_node) const {
+  std::vector<MuxEdgeId> edges;
+
+  VTR_ASSERT(valid_node_id(from_node));
+  VTR_ASSERT(valid_node_id(to_node));
+
+  for (const auto& edge : node_out_edges_[from_node]) {
+    for (const auto& cand : edge_sink_nodes_[edge]) {
+      if (cand == to_node) {
+        /* This is the wanted edge, add to list */
+        edges.push_back(edge);
+      }
+    }
+  }
+
+  return edges;
+}
 
 /* Find the number of levels in the MUX graph */
 size_t MuxGraph::num_levels() const {
@@ -95,6 +137,20 @@ size_t MuxGraph::num_memory_bits() const {
   return mem_ids_.size(); 
 }
 
+/* Find the mem that control the edge */
+MuxMemId MuxGraph::find_edge_mem(const MuxEdgeId& edge) const {
+  /* validate the edge */
+  VTR_ASSERT(valid_edge_id(edge));
+  return edge_mem_ids_[edge];
+}
+
+/* Identify if the edge is controlled by the inverted output of a mem */
+bool MuxGraph::is_edge_use_inv_mem(const MuxEdgeId& edge) const {
+  /* validate the edge */
+  VTR_ASSERT(valid_edge_id(edge));
+  return edge_inv_mem_[edge];
+}
+
 /* Find the sizes of each branch of a MUX */
 std::vector<size_t> MuxGraph::branch_sizes() const {
   std::vector<size_t> branch;
@@ -243,6 +299,15 @@ std::vector<MuxGraph> MuxGraph::build_mux_branch_graphs() const {
   return branch_graphs;
 } 
 
+/* Get the input id of a given node */
+MuxInputId MuxGraph::input_id(const MuxNodeId& node_id) const {
+  /* Validate node id */
+  VTR_ASSERT(valid_node_id(node_id));
+  /* Must be an input */
+  VTR_ASSERT(MUX_INPUT_NODE == node_types_[node_id]);
+  return node_input_ids_[node_id];
+}
+
 /* Get the node id of a given input */
 MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const {
   /* Use the node_lookup to accelerate the search */

vpr7_x2p/vpr/SRC/device/mux_graph.h

@@ -63,12 +63,20 @@ class MuxGraph {
   public: /* Public accessors: Data query */
     /* Find the number of inputs in the MUX graph */
     size_t num_inputs() const;
+    std::vector<MuxNodeId> inputs() const;
     /* Find the number of outputs in the MUX graph */
     size_t num_outputs() const;
+    std::vector<MuxNodeId> outputs() const;
+    /* Find the edge between two MUX nodes */
+    std::vector<MuxEdgeId> find_edges(const MuxNodeId& from_node, const MuxNodeId& to_node) const;
     /* Find the number of levels in the MUX graph */
     size_t num_levels() const;
     /* Find the number of SRAMs in the MUX graph */
     size_t num_memory_bits() const;
+    /* Find the mem that control the edge */
+    MuxMemId find_edge_mem(const MuxEdgeId& edge) const;
+    /* Identify if the edge is controlled by the inverted output of a mem */
+    bool is_edge_use_inv_mem(const MuxEdgeId& edge) const;
     /* Find the sizes of each branch of a MUX */
     std::vector<size_t> branch_sizes() const;
     /* Generate MUX graphs for its branches */
@@ -76,6 +84,8 @@ class MuxGraph {
     std::vector<MuxGraph> build_mux_branch_graphs() const; 
     /* Get the node id of a given input */
     MuxNodeId node_id(const MuxInputId& input_id) const;
+    /* Get the input id of a given node */
+    MuxInputId input_id(const MuxNodeId& node_id) const;
     /* Decode memory bits based on an input id */
     std::vector<size_t> decode_memory_bits(const MuxInputId& input_id) const;
   private: /* Private mutators : basic operations */

vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp

@@ -50,6 +50,32 @@ std::vector<BasicPort> ModuleManager::module_ports_by_type(const ModuleId& modul
   return ports;
 }
 
+/* Find the module id by a given name, return invalid if not found */
+ModuleId ModuleManager::find_module(const std::string& name) const {
+  if (name_id_map_.find(name) != name_id_map_.end()) {
+    /* Find it, return the id */
+    return name_id_map_.at(name); 
+  }
+  /* Not found, return an invalid id */
+  return ModuleId::INVALID();
+}
+
+/* Find the number of instances of a child module in the parent module */
+size_t ModuleManager::num_instance(const ModuleId& parent_module, const ModuleId& child_module) const {
+  /* validate both module ids */
+  VTR_ASSERT(valid_module_id(parent_module));
+  VTR_ASSERT(valid_module_id(child_module));
+  /* Try to find the child_module in the children list of parent_module*/
+  for (size_t i = 0; i < children_[parent_module].size(); ++i) {
+    if (child_module == children_[parent_module][i]) {
+      /* Found, return the number of instances */
+      return num_child_instances_[parent_module][i]; 
+    }
+  }
+  /* Not found, return a zero */
+  return 0;
+}
+
 /******************************************************************************
  * Public Mutators
  ******************************************************************************/
@@ -69,6 +95,7 @@ ModuleId ModuleManager::add_module(const std::string& name) {
   names_.push_back(name);
   parents_.emplace_back();
   children_.emplace_back();
+  num_child_instances_.emplace_back();
 
   port_ids_.emplace_back();
   ports_.emplace_back();
@@ -116,10 +143,14 @@ void ModuleManager::add_child_module(const ModuleId& parent_module, const Module
     parents_[child_module].push_back(parent_module);
   }
 
-  std::vector<ModuleId>::iterator child_it = std::find(children_[child_module].begin(), children_[child_module].end(), child_module);
+  std::vector<ModuleId>::iterator child_it = std::find(children_[parent_module].begin(), children_[parent_module].end(), child_module);
   if (child_it == children_[parent_module].end()) {
     /* Update the child module of parent module */
     children_[parent_module].push_back(child_module);
+    num_child_instances_[parent_module].push_back(1); /* By default give one */
+  } else {
+    /* Increase the counter of instances */
+    num_child_instances_[parent_module][child_it - children_[parent_module].begin()]++;
   }
 }
 

vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h

@@ -37,6 +37,9 @@ class ModuleManager {
     std::string module_name(const ModuleId& module_id) const;
     std::string module_port_type_str(const enum e_module_port_type& port_type) const;
     std::vector<BasicPort> module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const;
+    ModuleId find_module(const std::string& name) const;
+    /* Find the number of instances of a child module in the parent module */
+    size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const;
   public: /* Public mutators */
     /* Add a module */
     ModuleId add_module(const std::string& name);
@@ -55,6 +58,7 @@ class ModuleManager {
     vtr::vector<ModuleId, std::string> names_;                                  /* Unique identifier for each Module */
     vtr::vector<ModuleId, std::vector<ModuleId>> parents_;                 /* Parent modules that include the module */
     vtr::vector<ModuleId, std::vector<ModuleId>> children_;                /* Child modules that this module contain */
+    vtr::vector<ModuleId, std::vector<size_t>> num_child_instances_;          /* Number of children instance in each child module */
 
     vtr::vector<ModuleId, vtr::vector<ModulePortId, ModulePortId>> port_ids_;    /* List of ports for each Module */ 
     vtr::vector<ModuleId, vtr::vector<ModulePortId, BasicPort>> ports_;    /* List of ports for each Module */ 

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c

@@ -159,7 +159,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
   MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch);
 
   /* 0. basic units: inverter, buffers and pass-gate logics, */
-
   /* Check if the routing architecture we support*/
   if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) {
     vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable Verilog dumping only support uni-directional routing architecture!\n");

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp

@@ -92,6 +92,10 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma
   BasicPort mem_inv_port("mem_inv", num_mems);
   module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
 
+  /* Get the module id of tgate in Module manager */
+  ModuleId tgate_module_id = module_manager.find_module(circuit_lib.model_name(tgate_model));
+  VTR_ASSERT(ModuleId::INVALID() != tgate_module_id);
+
   /* dump module definition + ports */
   print_verilog_module_declaration(fp, module_manager, module_id);