7eeb35d21f
[Script] Bug fix in yosys script to synthesis BRAM
2021-03-17 15:12:04 -06:00
1976a8068f
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
2021-03-17 15:11:17 -06:00
deee7ba366
[Script] Add example script to run vtr benchmarks
2021-03-17 15:10:56 -06:00
910f8471dd
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
2021-03-17 15:10:05 -06:00
76113a80fa
[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
2021-03-17 15:09:12 -06:00
e1f8b252b1
Merge branch 'master' into yosys_heterogeneous_block_support
2021-03-16 20:05:21 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
094b3e9b90
[Script] Use parameters in template yosys script supporting BRAMs
2021-03-16 19:51:48 -06:00
cea43c2c45
[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
2021-03-16 18:04:31 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
84778bd38d
[Script] Add new yosys script to support architectures with BRAMs
2021-03-16 16:52:18 -06:00
090f483a11
[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
2021-03-16 16:45:57 -06:00
76837e02e6
[Script] Rename yosys script supporting bram and restructure techlib files
2021-03-16 16:16:53 -06:00
e61857aa2b
Merge branch 'master' into ganesh_dev
2021-03-11 19:17:02 -07:00
366bec232c
[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
2021-03-11 15:25:48 -07:00
bb2a02c9ad
[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[ https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v ]
2021-03-11 15:23:14 -07:00
baf162e401
[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
2021-03-10 22:45:19 -07:00
a6186db315
[Test] Update bitstream annotation with new syntax
2021-03-10 20:45:17 -07:00
7d07f5d8cb
[Test] Update bitstream setting example with mode bit overwriting
2021-03-10 15:34:53 -07:00
b42541d84e
[Flow] Support multiple iterations in rewriting yosys scripts
2021-03-10 14:10:35 -07:00
90a00da1df
[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
2021-03-10 13:56:35 -07:00
d21909ad6c
[Test] Use custom rewriting script in lut_adder test
2021-03-10 13:48:20 -07:00
0e772bc3b4
[Script] Patch the yosys rewrite script to avoid existing blif outputs
2021-03-10 13:47:30 -07:00
7adb78b159
[Script] Add a template yosys script with rewriting at the end
2021-03-10 13:40:31 -07:00
035043d0d8
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
2021-03-10 13:36:11 -07:00
5d46537b5b
[Script] Allow users to specify custom post-synthesis verilog for simulation
2021-03-10 11:45:55 -07:00
aafd87c3f9
[Flow] Update flow-run to support custom yosys rewrite scripts
2021-03-10 11:36:29 -07:00
db8ea86b2f
update tests to use no_ff_map and remove tests that need async set/reset for now
2021-03-10 10:04:45 -08:00
608bd1f658
comment out desings that utilize local async reset/preset
2021-03-09 19:24:01 -08:00
7f4c20ff33
comment out desings that utilize local async reset/preset
2021-03-09 10:37:06 -08:00
c4b83aeaa9
bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
2021-03-09 00:46:40 -08:00
2daa770319
[Arch] Update openfpga architecture to include quicklogic cell sim
2021-03-08 21:40:29 -07:00
812d8c950e
[Script] Update quicklogic's script to output correct verilog file name
2021-03-08 21:39:44 -07:00
37aa42d305
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
2021-03-08 21:38:51 -07:00
c53c41b7a5
[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
2021-03-08 21:09:23 -07:00
131643dcc0
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
2021-03-08 21:08:55 -07:00
b860722893
Fixed parameter ys_rewrite_params name bug
2021-03-08 10:34:39 -07:00
52de55e7eb
Merge branch 'master' into ganesh_dev
2021-03-08 10:15:06 -07:00
906d2fa72d
Merge branch 'master' into shift_reg
2021-03-08 09:24:29 -07:00
7a35811430
[Flow] Yosys rewrite support
2021-03-08 00:35:47 -07:00
67cd9a69b7
[Flow] Extended yosys variable subtitution
2021-03-08 00:21:07 -07:00
7945628307
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
2021-03-07 22:25:01 -08:00
6a1ce01084
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
2021-03-07 22:02:11 -08:00
ce76c58422
add shift register test case
2021-03-05 09:06:05 -08:00
2b2acae757
Adding command to generate verilog file out of yosys run
2021-03-05 04:07:02 -08:00
0cbad747a1
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
2021-03-04 01:10:47 -08:00
817729ac86
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
2021-03-01 22:31:15 -08:00
e34380a654
Merge branch 'master' into default_net_type
2021-03-01 08:38:58 -07:00
ea4aee8cb2
For time-being yosys script running in no_adder mode.
2021-02-28 22:07:23 -08:00
0038496d9c
Replacing -openfpga with -family qlf_k4n8
2021-02-28 21:08:47 -08:00
b4b6ada06f
[Script] Correct bugs in example scripts using default_net_type
2021-02-28 16:31:44 -07:00
86930d63d3
[Test] Deploy new test to CI
2021-02-28 16:18:46 -07:00
b90a17543d
[Test] Add new test case to test default nettype in different verilog syntax
2021-02-28 16:16:45 -07:00
9f4d05da67
[Test] Bug fix for new test case
2021-02-28 16:11:30 -07:00
8cc2c7d924
[Script] Bug fix for default net type example script
2021-02-28 12:35:44 -07:00
6d419fed41
[Test] Deploy verilog default net wire type test case to CI
2021-02-28 12:33:48 -07:00
18a7041424
[Test] Add default net type test for explicit port mapping
2021-02-28 12:31:32 -07:00
0723b79bce
[Script] Add example script for verilog default net type
2021-02-28 12:29:56 -07:00
27200e3daa
[Test] Update regression test cases for fpga verilog
2021-02-28 12:24:36 -07:00
ff29cc3dff
[Test] Move tests to a test group
2021-02-28 12:23:35 -07:00
9cb1ca42fe
[Test] Deploy default net type option to test case
2021-02-28 12:20:43 -07:00
ae05871b1f
[Script] Remove default net type from an example script; Limit it to some test cases
2021-02-28 12:19:14 -07:00
d7eb159726
[Script] Add default net type option to example openfpga shell scripts
2021-02-28 12:08:30 -07:00
0d82e4939c
[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
2021-02-26 09:35:40 -07:00
744d87cb4e
[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
2021-02-26 09:34:52 -07:00
870d3a0e27
Merge branch 'master' into dev
2021-02-26 09:28:42 -07:00
1082d3c677
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
2021-02-25 23:39:07 -08:00
1e48d4f6dc
Modifying custom yosys script file name
2021-02-25 22:21:39 -08:00
4c2a88e27f
[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed
2021-02-24 11:51:10 -07:00
0ce9b66c75
[Arch] Add a dummy adder lut circuit model to support HDL simulation
2021-02-24 10:09:44 -07:00
86a602d381
[Test] Deploy new test to CI
2021-02-23 19:55:07 -07:00
a62786986b
[Test] Turn off verification in adder lut test temporarily
2021-02-23 19:03:25 -07:00
ad25944e59
[Arch] Patched superLUT architecture example when trying adder8 synthesis script
2021-02-23 19:00:27 -07:00
53df7f69e7
[Test] Bug fix in the test case using lut adder
2021-02-23 16:59:46 -07:00
db71cc8a16
[Test] Add LUT adder test using quicklogic synthesis script
2021-02-23 16:50:58 -07:00
19f6b221b1
[Test] Rework comments on runtime
2021-02-22 15:25:57 -07:00
4803b0ce42
[Test] Add test case for sdc controller
2021-02-22 15:02:14 -07:00
c7a9a4e896
[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
2021-02-22 15:01:50 -07:00
ca135f3325
[Arch] Add flagship architecture with 8-clock
2021-02-22 15:01:18 -07:00
2e2b1cb6e7
[Test] Use hetergenenous FPGA architecture in quicklogic tests
2021-02-22 13:41:04 -07:00
1c09c55e9f
[Arch] Add hetergenenous 8-clock FPGA architecture
2021-02-22 13:38:50 -07:00
b3fed683f9
[Test] Deploy test to CI
2021-02-22 12:43:30 -07:00
bc30f62c5a
[Test] Add test for sdc controller
2021-02-22 12:41:53 -07:00
60dc194d8f
[Test] Bug fix in the 5clock test case
2021-02-22 11:46:23 -07:00
71e0026a50
[Test] Add new test for 5-clock counter to quicklogic tests
2021-02-22 11:32:17 -07:00
2bb588dacf
[Flow] Add a new script for generating bitstream for multi-clock architectures
2021-02-22 11:31:24 -07:00
77896379e2
[Arch] Add simulation setting for 8-clock architectures
2021-02-22 11:10:03 -07:00
16debe49f6
[Arch] Add more comments on the 4 clock simulation setting file
2021-02-22 11:04:34 -07:00
0ac75723af
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
b9c2564a7e
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
2021-02-22 10:49:21 -07:00
bc8aa0ebc6
[Test] Remove routing test from quicklogic's flow test
2021-02-22 10:22:47 -07:00
2dbdc2644f
[Benchmark] Remove replicate micro benchmarks
2021-02-22 10:22:19 -07:00
9b6b2068ee
[Test] Move MCNC test to benchmark sweep test group
2021-02-22 10:18:34 -07:00
c1f4a434e4
[Doc] Update README for the regression test tasks
2021-02-22 10:17:02 -07:00
d6a02a985e
Merge pull request #248 from lnis-uofu/add_quicklogic_tests
...
Disabling verilog testbench generation for quicklogic tests
2021-02-22 09:02:29 -07:00
d842026672
Disabling verilog testbench generation for quicklogic tests
2021-02-21 21:58:23 -08:00
be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
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Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
576e6753f6
Removing 2 more tests which are variant of and design
2021-02-19 09:11:19 -08:00
d4c5a5655a
Removing blif file as well as and2 testcase
2021-02-19 08:55:17 -08:00
6de0954ca5
Uncommenting all benchmarks except 2 that requires multiple clocks
2021-02-19 08:40:26 -08:00
e08ac1a41e
[Test] Deploy synthesizable verilog test to CI
2021-02-18 19:37:45 -07:00
e19fc15fec
[Test] bug fix in test case
2021-02-18 19:37:45 -07:00
affc8cbbc4
[Test] Deploy test to CI
2021-02-18 19:37:45 -07:00
2e88b035ed
[Test] Add wire LUT repacker test case
2021-02-18 19:37:44 -07:00
1f097abe99
[Benchmark] Add micro benchmark for FIR filter
2021-02-18 19:37:44 -07:00
69cdc11ea5
Uncommenting the tests that are running fine
2021-02-18 04:17:12 -08:00
d85d6e964e
Merge pull request #227 from watcag/master
...
Standard-cell flow
2021-02-17 10:11:34 -07:00
7ee01711c2
Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
2021-02-17 00:06:59 -08:00
44a979288b
Adding quicklogic tests and updating the corresponding conf file to run them
2021-02-16 23:08:38 -08:00
a819375f69
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
2021-02-16 16:53:13 -07:00
2c2e493739
[Test] Remove quicklogic test from basic tests
2021-02-16 12:29:10 -07:00
9c19e2b365
[Test] Move regression test scripts from workflow to openfpga_flow
2021-02-16 11:55:47 -07:00
426b6449d8
change the test to turn off power analysis
2021-02-15 02:45:38 -08:00
3a587f663a
copy yosys output file in case power analysis setting is off
2021-02-15 02:36:02 -08:00
e683e00032
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
2021-02-10 14:50:11 -07:00
9b86f3bb85
Merge branch 'master' into dev
2021-02-09 22:40:45 -07:00
22e675148e
[HDL] Add HDL codes for a super LUT with embedded carry logic
2021-02-09 21:13:22 -07:00
b81b74aa7c
[Arch] Patch architecture to support superLUT-related XML syntax
2021-02-09 20:23:32 -07:00
7dcc14d73f
[Arch] Bug fix in the example arch with super LUT
2021-02-09 15:52:22 -07:00
3ae501a5ea
[Test] Update test case to use dedicated eblif file
2021-02-09 15:51:57 -07:00
1712ee4edb
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
2021-02-09 15:41:21 -07:00
4c7f4bd82f
ahoy nice
2021-02-09 17:38:19 -05:00
2b51b36dd6
[Test] Now use the super LUT arch in the test case
2021-02-09 15:27:44 -07:00
56284059de
[Test] Add a test case for a super LUT
2021-02-09 15:25:32 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
71c76df063
default to ns for time unit -- synopsys dc whines
2021-02-09 17:08:38 -05:00
6bb2e29f17
default to ns for time unit -- synopsys dc whines
2021-02-09 17:04:52 -05:00
87c69460df
what is going on
2021-02-09 11:33:08 -05:00
cc74c6268a
trying fix chan width
2021-02-09 11:28:19 -05:00
95fe4d7dae
adding dff synth
2021-02-09 10:34:54 -05:00
b14b5f975d
adding sweep for W
2021-02-09 08:48:25 -05:00
d7967da328
bugfix in alt
2021-02-08 23:04:00 -05:00
485708423c
no need for dff*, but need tap_buf4
2021-02-08 23:00:13 -05:00
cf154d8bb9
no need for dff*, but need tap_buf4
2021-02-08 22:29:55 -05:00
e14c0bf0c4
no need for dff*, but need tap_buf4
2021-02-08 22:28:42 -05:00
45437fbc46
no need for dff*, but need tap_buf4
2021-02-08 22:27:57 -05:00
853bf8af43
typos fixed;
2021-02-08 22:03:14 -05:00
d040ba569c
merge for consideration;
2021-02-08 21:29:34 -05:00
94f858fcde
merge for consideration;
2021-02-08 21:27:01 -05:00
0c6d27cf7e
merge for consideration;
2021-02-08 21:26:48 -05:00
b4185f7e8c
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
2021-02-08 21:11:30 -05:00
2344cdcabc
merge
2021-02-08 21:11:28 -05:00
1ce94040da
Merge pull request #221 from lnis-uofu/flow_dev
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[Flow] Support multi-user environment for running task
2021-02-08 12:43:57 -07:00
80a4872ba0
Merge pull request #222 from lnis-uofu/gg_cleanup
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[Flow] ACE is optional during flow script, only runs when power estimation is on
2021-02-08 10:08:47 -07:00
ede5f8ed58
[Flow] Support multi-user enviroment for running task
2021-02-07 22:11:04 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
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Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
ee14c15e58
Merge pull request #212 from lnis-uofu/soft_adder_lut_support
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Support overloading LUT bitstream from attributes in .eblif file format
2021-02-04 21:55:02 -07:00
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
dc09c47411
[Arch] Remove packable from architecture files and replace with disable_packing
2021-02-04 18:03:56 -07:00
224bf6c686
Merge branch 'master' into dev
2021-02-04 17:21:15 -07:00
66bc370c4d
[Arch] Use disable_packing in architecture library
2021-02-04 16:29:03 -07:00
a4c266d59a
[Arch] Add pack patterns for soft adders; Still fail in packing
2021-02-03 19:11:15 -07:00
6cdc31f073
[Flow] ACE is optional duign flow script
2021-02-03 19:07:48 -07:00
cac1160bf7
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
2021-02-03 11:20:56 -07:00
df4a397470
[Cleanup] Removed deadcode
2021-02-03 10:35:14 -07:00
4c825b27b3
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
31441c0b64
[Test] Deploy adder_8 to soft adder test
2021-02-03 09:26:38 -07:00
05d63567d0
[Benchmark] Use latest adder eblif file
2021-02-03 09:21:38 -07:00
ebe66dea35
Bumping up latest yosys changes related to adder tech mapping
2021-02-03 14:30:06 +05:30
2c06960e4f
[Benchmark] Add subckt definition to micro benchmark and2.eblif
2021-02-02 15:51:16 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
dc320182b0
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
2021-02-02 15:04:43 -07:00
8e36ed1ab6
[Test] Update task configuration to use and2 eblif
2021-02-02 15:01:15 -07:00
62803dc044
[Benchmark] Add eblif example for and2 benchmark
2021-02-02 14:59:31 -07:00
5e2847bc41
[Test] Update test case to use eblif file
2021-02-02 09:33:41 -07:00
39e6f62d91
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
d3397f6936
[Script] Remove activity from bitstream setting example script
2021-02-02 09:25:36 -07:00
9ff5e7926b
[Test] Update test case to use the adder benchmark
2021-02-02 09:24:39 -07:00
7f14dfbe87
[Script] Add example script to use bitstream setting
2021-02-02 09:18:08 -07:00
04594cb7ab
[Test] Adapt bitstream annotatin file to parser's requirement
2021-02-01 17:38:36 -07:00
280c9620aa
[Test] Add an example bitstream annotation file
2021-02-01 16:01:21 -07:00
a6354fab7c
[Arch] Decide to move external bitstream definition to a separated XML file
2021-02-01 15:57:44 -07:00
df88e2adc0
[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
2021-02-01 14:26:11 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
7f0f7a1c70
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
b215b868c1
[HDL] Bug fix in HDL netlist due to port name mismatching
2021-02-01 11:35:25 -07:00
e4abe263c3
[Arch] Bug fix
2021-02-01 11:29:27 -07:00
fb05e1a938
[Arch] bug fix due to using openfpga cell library
2021-02-01 11:27:21 -07:00
940dce469a
[Test] Bug fix for test case configuration
2021-02-01 11:19:47 -07:00
a80acfb547
[Test] Add new test case to CI script
2021-02-01 11:16:12 -07:00
af630dab1e
[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
2021-02-01 10:53:38 -07:00
9cce411eda
[Test] Add adder test cases
2021-02-01 10:42:24 -07:00
0eb949b85a
[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
2021-02-01 10:34:32 -07:00
e0e2506e32
[HDL] Remove redundant comments
2021-02-01 10:33:08 -07:00
39543f7945
[HDL] Add carry mux2 to cell library
2021-02-01 10:23:46 -07:00
6ede799c16
[Arch] Add openfpga architecture for the QLSOFA
2021-02-01 10:15:35 -07:00
df05911d24
Merge branch 'master' into soft_adder_lut_support
2021-02-01 10:02:05 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
a70725b4be
Merge branch 'master' into dev
2021-01-29 11:41:40 -07:00
8b74947737
[Script] Now multi-clock openfpga shell script no longer needs activity file
2021-01-29 11:40:33 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
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* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
0b82b6439b
[Regression] Upgraded runtime enviroment to python3.8
2021-01-26 16:40:45 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
3fdd5ae8b3
[Script] Use pin constraints in template script
2021-01-19 17:42:25 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
12e0efd03e
[Script] Add an example openfpga script to use repack design constraints
2021-01-17 10:33:56 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
89f9d24d32
[Flow] Update simulation settings for multiple clock to allow unique clock port name
2021-01-15 10:35:43 -07:00
dbed04b53b
[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
2021-01-14 15:42:21 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
923f3a3401
[Flow] Add an example simulation settings for a 4-clock FPGA fabric
2021-01-13 17:29:39 -07:00
9a906e787b
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
2021-01-13 15:43:31 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
c5a2027f36
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
2021-01-13 15:41:48 -07:00
7af6d7f07d
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
2021-01-13 15:38:44 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
ccf3e037ff
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
2021-01-13 13:31:06 -07:00
250adb01cf
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
2021-01-13 13:18:31 -07:00
99e2a068fb
[Test] Add a test case for multi-clock
2021-01-12 18:06:25 -07:00
2f1aceda67
[Doc] Update documentation about architecture naming rules
2021-01-12 18:01:24 -07:00
9fa49c401c
[Arch] Add openfpga architecture which uses 4 global clocks
2021-01-12 18:00:22 -07:00
16b4e89326
[Doc] Update documentation for VPR architectures
2021-01-12 17:57:40 -07:00
7ccdff4543
[Arch] Add an architecture using 4 clocks
2021-01-12 17:55:57 -07:00
3790f2c26a
[Benchmark] Add 2-clock micro benchmark
2021-01-12 17:48:52 -07:00
a0b9f2b40d
Merge pull request #170 from lnis-uofu/dev
...
Extended Support on Defining Global Ports from Physical Tile Ports
2021-01-11 10:02:31 -07:00
e58e1e86c2
[Test] Update test case to use new shell script
2021-01-10 11:09:10 -07:00
18d2a8ce19
[Flow] Add new script for fixed device layout using global tile clock
2021-01-10 11:08:02 -07:00
aaf582acc5
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
1c68e43acf
[Test] Add new test case for registerable I/O architecture
2021-01-10 11:00:21 -07:00
f21d22f691
[Doc] Update README for new architectures
2021-01-10 10:54:59 -07:00
dfb3e32147
[Arch] Add openfpga archiecture for registerable I/O
2021-01-10 10:54:41 -07:00
853e7b1a40
[Arch] Add vpr architecture where I/O can be either combinational or registered
2021-01-10 10:54:09 -07:00
43418cd76b
[Test] Deploy pipeplined and2 to test cases
2021-01-10 10:28:22 -07:00
6521aa2e7a
[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 10:27:59 -07:00
4412bbd084
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 10:21:30 -07:00
0b74575606
[Arch] Update arch using global reset tile port
2021-01-09 18:04:55 -07:00
7b24da267a
[Arch] Remove port size XML syntax
2021-01-09 16:30:46 -07:00
9f12b25a24
[Arch] Add port size to global port defined thru tile annotation
2021-01-09 16:23:28 -07:00
0f5f0a3527
[Arch] Add x,y coordinates to global port definition
2021-01-09 15:50:09 -07:00
a14a56772a
[Arch] Introduce new XML syntax for global port in tile annotation
2021-01-09 15:48:42 -07:00
8a5741b1ae
Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
2021-01-08 07:08:24 -08:00
a813c9016b
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
2021-01-04 17:39:13 -07:00
06af30ef10
[Test] Add test case for the SCFF usage in configuration chain
2021-01-04 17:30:19 -07:00
709ee1b842
[HDL] Update dff netlist for SCFF used in configuration chain
2021-01-04 17:17:35 -07:00
c97a92d628
[Arch] Patch openfpga architecture for ccff circuit model port requirement
2021-01-04 17:15:50 -07:00
294ad97d38
[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
2021-01-04 14:56:49 -07:00
722a9bcf63
[HDL] Add scan-chain DFF cell with configuration enable signal
2021-01-04 14:31:26 -07:00
2484721a45
Updating write_verilog_testbench by removing option explicit_port_mapping
2020-12-22 22:17:50 -08:00
3c9e4919b4
Updating variable name in ys to call BLIF output file.
2020-12-18 03:18:46 -08:00
1f994319fd
Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
2020-12-16 04:19:56 -08:00
891e2f8aa3
Adding arch xml from SOFA repo. Also updating the script with its file location
2020-12-16 04:14:18 -08:00
0ee3efb306
Adding a testcase to run yosys quicklogic flow
2020-12-10 02:41:43 -08:00
tangxifan
Tarachand Pagarani
ganeshgore
Lalit Sharma
Lalit Narain Sharma
Nachiket Kapre
AurelienAlacchi