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Author SHA1 Message Date
N. Engelhardt 9c7f0e7670 show: truncate very long module names 2023-06-20 12:53:56 +02:00
N. Engelhardt 22c9237716 show: escape angle brackets 2023-06-20 11:17:12 +02:00
N. Engelhardt 7c606bd5a3
Merge pull request #3791 from nakengelhardt/nak/show_attr_wires 2023-06-05 16:18:54 +02:00
N. Engelhardt 6f5d984bdb
Merge pull request #3778 from jix/yw_clk2fflogic 2023-06-05 16:15:04 +02:00
N. Engelhardt 0707b911c7 show: add -viewer none option 2023-06-01 11:00:07 +02:00
N. Engelhardt 4b986c9c65 fix wire color after BUF 2023-05-31 17:38:46 +02:00
N. Engelhardt 26555a998d show -colorattr: extend colors to arrows when wires have attribute 2023-05-26 17:18:21 +02:00
Eddie Hung ec8d7b1c68 abc9_ops -prep_hier to unmap entire module 2023-05-25 18:42:08 +01:00
Jannis Harder e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses 
This makes clk2fflogic add an attr to $ff cells that carry the state of
the emulated async FF. The $ff output doesn't have any async updates
that happened in the current cycle, but the $ff input does, so the $ff
input corresponds to the async FF's output in the original design.

Hence this patch also makes the following changes to passes besides
clk2fflogic (but only for FFs with the clk2fflogic attr set):

  * opt_clean treats the input as a register name (instead of the
    output)

  * rename -witness ensures that the input has a public name

  * the formal backends (smt2, btor, aiger) will use the input's
    name for the initial state of the FF in witness files

  * when sim reads a yw witness that assigns an initial value to the
    input signal, the state update is redirected to the output

This ensures that yosys witness files for clk2fflogic designs have
useful and stable public signal names. It also makes it possible to
simulate a clk2fflogic witness on the original design (with some
limitations when the original design is already using $ff cells).

It might seem like setting the output of a clk2fflogic FF to update the
input's initial value might not work in general, but it works fine for
these reasons:

  * Witnesses for FFs are only present in the initial cycle, so we do
    not care about any later cycles.

  * The logic that clk2fflogic generates loops the output of the
    genreated FF back to the input, with muxes in between to apply any
    edge or level sensitive updates. So when there are no active updates
    in the current gclk cycle, there is a combinational path from the
    output back to the input.

  * The logic clk2fflogic generates makes sure that an edge sensitive
    update cannot be active in the first cycle (i.e. the past initial
    value is assumed to be whatever it needs to be to avoid an edge).

  * When a level sensitive update is active in the first gclk cycle, it
    is actively driving the output for the whole gclk cycle, so ignoring
    any witness initialization is the correct behavior.
 2023-05-25 12:48:02 +02:00
Jannis Harder 7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization 2023-05-25 12:46:16 +02:00
gatecat 52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
Jannis Harder ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs 
When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
 2023-05-18 16:50:11 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை) 693c609eec
Merge branch 'YosysHQ:master' into main/issue2525 2023-05-16 21:21:32 -07:00
Muthu Annamalai 665e0f6131 remove new line per maintainer request 2023-05-17 04:20:13 +00:00
Miodrag Milanović acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498 
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
 2023-05-15 16:34:35 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை) c855502bd5
Update passes/techmap/libparse.cc 
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498

Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
 2023-05-09 06:40:21 -07:00
Miodrag Milanović 226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff 
Updated the `plugin` command to better handle paths
 2023-05-09 08:46:02 +02:00
N. Engelhardt 266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00
Krystine Sherwin 5a4e72f57a
Fix sim writeback check for yw_cosim 
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
 2023-05-08 13:13:09 +12:00
Muthu Annamalai 17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest 2023-05-06 23:37:47 -07:00
Miodrag Milanović 4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop 
Synthesizable properties
 2023-05-05 11:03:09 +02:00
Muthu Annamalai 81e089cb60 [YOSYS-2525] fix read_liberty newline handling #2525 
- newlines can be allowed in function parsing
 2023-05-04 22:30:27 -07:00
Aki Van Ness bb240665b7
plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support 2023-05-03 03:35:55 -04:00
Aki Van Ness 572c8df9a8
plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with `.so.so` on the end 2023-05-03 02:22:46 -04:00
Jannis Harder 7bff8b63b3 rename: Fix renaming cells in -witness mode 
This was renaming cells while iterating over them which would always
cause an assertion failure. Apparently having to rename cells to make
all witness signals public is rarely required, so this slipped through.
 2023-04-25 12:39:00 +02:00
Benjamin Barzen 8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2023-04-22 16:24:36 -07:00
N. Engelhardt 57897927ff stat: pass down quiet arg 2023-02-28 17:12:55 +01:00
Miodrag Milanović 21e87f7986
Merge pull request #3646 from YosysHQ/lofty/fix-3591 
muxcover: do not add decode muxes with x inputs
 2023-02-27 16:26:57 +01:00
Jannis Harder 1c667fab2b
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes 
sim: For yw cosim, drive parent module's signals for input ports
 2023-02-15 13:45:00 +01:00
N. Engelhardt b562b54c14 dfflegalize: allow setting mince and minsrst args from scratchpad 2023-02-15 12:53:46 +01:00
Jannis Harder ec94703619
Merge pull request #2995 from georgerennie/cover_precond 
chformal: Add -coverenable option
 2023-02-14 17:46:31 +01:00
Jannis Harder 85f611fb23
Merge pull request #3126 from georgerennie/equiv_make_assertions 
equiv_make: Add -make_assert option
 2023-02-14 17:15:55 +01:00
Jannis Harder b636af9751 chformal: Note about using -coverenable with the Verific frontend 2023-02-14 17:10:43 +01:00
Miodrag Milanovic 550a5b7b6b Update license 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 713b7d3e26 added support for latched output reset 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 131b557727 Initial implementation of synthesizable assertions 2023-02-13 17:23:26 +01:00
Jannis Harder 1698202ccc sim: For yw cosim, drive parent module's signals for input ports 2023-02-13 12:26:06 +01:00
Miodrag Milanovic 5f33c0e0b2 Updated changelog 2023-02-08 10:11:47 +01:00
N. Engelhardt 417fadbefd
Merge pull request #3625 from povik/show_cleanup 2023-02-06 16:11:26 +01:00
N. Engelhardt 419f91a2b9 add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
N. Engelhardt ecfa7e9fbc add pmux option to bmuxmap for better fsm detection with verific frontend 2023-01-30 16:12:53 +01:00
Lofty 822c7b0341 muxcover: do not add decode muxes with x inputs 2023-01-26 05:19:45 +00:00
Jannis Harder afac3f2c76 formalff: Fix crash with _NOT_ gates in -hierarchy mode 2023-01-25 12:55:29 +01:00
Miodrag Milanović 8180cc4325
Merge pull request #3624 from jix/sim_yw 
Changes to support SBY trace generation with the sim command
 2023-01-23 16:55:17 +01:00
Miodrag Milanović 245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes 
Fixes for some of clang scan-build detected issues
 2023-01-23 16:24:22 +01:00
gatecat bfacaddca8 show: Remove left-in debug log_warning 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-23 13:54:07 +01:00
Claire Xenia Wolf bfc3c20cfb Improve splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2023-01-18 00:31:29 +01:00
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Martin Povišer f9e30ee5e0 passes: show: s/pos/bitpos/ for readability 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 314b864205 passes: show: Reuse string parts in generation of portboxes 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 61abca10a3 passes: show: Touch chunk iteration in gen_portbox 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 60318a5cd8 passes: show: Label no_signode flag 
Label the flag and rearrange the control flow a bit.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 8b1f5fba62 passes: show: Simplify wire bit range logic 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer ad149cc42a passes: show: Factor out 'join_label_pieces' 
In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 5848790835 passes: show: Label signed_suffix flag 
To make it easier to follow what's going on.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 13700e12e5 passes: show: s/idx/dot_idx/ for readability 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer e3709ce776 passes: show: Fix portbox bit ranges in case of driven signals 
When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.

So, taking for example the following Verilog snippet,

  module DRIVER (Q);
     output [7:0] Q;
     assign Q = 8'b10101010;
  endmodule

  module main;
     wire w;
     DRIVER driver(.Q({8{w}}));
  endmodule

make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Jannis Harder d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder 7ddec5093f sim: Improvements and fixes for yw cosim 
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
 2023-01-11 18:07:16 +01:00
Jannis Harder dda972a148 sim: New -append option for Yosys witness cosim 
This is needed to support SBY's append option.
 2023-01-11 18:07:16 +01:00
Jannis Harder 2dd5652215 sim: Add Yosys witness (.yw) cosimulation 2023-01-11 18:07:16 +01:00
Jannis Harder f6458bab70 sim: Only check formal cells during gclk simulation updates 
This is required for compatibility with non-multiclock formal semantics.
 2023-01-11 18:07:16 +01:00
Jannis Harder 9c6198a827 sim: Internal API to set $initstate 
This is not yet added to any of the simulation drivers.
 2023-01-11 18:07:16 +01:00
Jannis Harder 44b26d5c6d sim: Emit used memory addresses as signals to output traces 
This matches the behavior of smtbmc.

This also updates the sim internal memory API to allow masked writes
where State::Sa bits (internal don't care - not a valid value for a
signal) leave the memory content unchanged.
 2023-01-11 18:07:16 +01:00
Jannis Harder 5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef 
This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
 2023-01-11 18:07:16 +01:00
N. Engelhardt 4173daa708
Merge pull request #3605 from gadfort/stat-json-area 2023-01-11 16:41:44 +01:00
Claire Xen 843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
 2023-01-11 16:26:04 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf 6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
Miodrag Milanovic e3c0fd8b10 qbfsat support for cvc5, fixes #3608 2023-01-09 16:14:01 +01:00
Peter Gadfort 58cca9592d stat: ensure area is included in json output 
Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
 2022-12-29 21:51:46 -05:00
Claire Xenia Wolf 029b0aac7f Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-21 14:50:23 +01:00
Claire Xenia Wolf 1bc832a8e1 Allow non-unique modules without state in sim writeback-mode 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:43:02 +01:00
Claire Xenia Wolf a9072dc23c Small bugfix in uniquify pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:41:48 +01:00
Jannis Harder 4a0ed35aab xprop: Improve signal splitting code 
Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
 2022-12-12 17:51:01 +01:00
Claire Xenia Wolf 6a6e1d8424 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-09 18:28:17 +01:00
Jannis Harder 967529abb1 formalff: Proper error messages on async inputs for the -clk2ff mode 2022-12-09 15:25:40 +01:00
Claire Xenia Wolf dc14def5f3 Add gold-x handing to miter cross port handling 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-08 22:14:16 +01:00
Claire Xenia Wolf 3454bddbe2 Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-08 20:06:23 +01:00
Jannis Harder 172a8e79f0 xprop: Add -split-public option 2022-12-08 20:00:01 +01:00
Claire Xenia Wolf 068031d2aa Improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-07 16:10:58 +01:00
Claire Xenia Wolf aeba966475 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-07 12:46:49 +01:00
Claire Xenia Wolf c679b408cb Various improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-06 16:43:01 +01:00
Claire Xenia Wolf 2895a66784 Bugfix in splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-06 16:00:48 +01:00
Claire Xenia Wolf e151e44caa Improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 19:32:31 +01:00
Claire Xenia Wolf c9f4b06cb2 Add "viz" pass for visualizing big-picture data flow in larger designs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 11:35:10 +01:00
Claire Xenia Wolf 92fc6cd4a9 Add splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 01:33:04 +01:00
Jannis Harder 7036a312bf stat: Fix JSON output for empty designs 2022-12-02 14:36:19 +01:00
Jannis Harder ed02d52f30 tee: Allow logging command output to a given scratchpad value 2022-12-02 14:36:19 +01:00
Claire Xenia Wolf 956b7f5fd1 Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff 2022-12-01 11:31:39 +01:00
Claire Xenia Wolf fbf8bcf38f Add insbuf -chain mode 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-01 10:02:35 +01:00
Jannis Harder eb0039848b miter: Add -make_cover option to cover each output pair difference 2022-11-30 19:01:28 +01:00
Jannis Harder 551ca7f97f formalff: Fix -ff2anyinit assertion error for fine FFs 2022-11-30 19:01:28 +01:00
Jannis Harder ce708122a5 New xprop pass to encode 3-valued x-propagation using 2-valued logic 2022-11-30 19:01:28 +01:00
Jannis Harder 5ff69a0fe2 sim: Improved global clock handling 2022-11-30 18:50:53 +01:00
Jannis Harder 3ecf85e32c opt_expr: Optimizations for `$bweqx` and `$bwmux` 2022-11-30 18:50:53 +01:00
Jannis Harder be752a20dc Add bwmuxmap pass 2022-11-30 18:50:53 +01:00
Jannis Harder 7203ba7bc1 Add bitwise `$bweqx` and `$bwmux` cells 
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
 2022-11-30 18:24:35 +01:00
Jannis Harder 1e67c3a3c2 opt_expr: Fix shift/shiftx optimizations 2022-11-30 18:24:25 +01:00
Jannis Harder fd56d1f79e opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells 2022-11-29 19:06:45 +01:00
Jannis Harder c08242ba41 opt_expr: Optimize bitwise logic ops with one fully const input 2022-11-29 19:06:45 +01:00
Jannis Harder 661fa5ff92 simplemap: Map `$xnor` to `$_XNOR_` cells 
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
 2022-11-29 19:06:45 +01:00
Jannis Harder ed0e14820e sat: Add -set-def-formal option to force defined $any* outputs 2022-11-28 14:50:52 +01:00
Miodrag Milanovic b0be19c126 Support importing verilog configurations using Verific 2022-11-25 13:02:11 +01:00
N. Engelhardt b64141f48b mention prerequisites in fsm_detect and fsm help 2022-11-21 16:07:23 +01:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496) 
Rst docs conversion
 2022-11-15 12:55:22 +01:00
Jannis Harder 9b4fba3870 sim: Run a comb-only update step to set past values during FST cosim 
The previous approach only initialized past_d and past_ad while for FST
cosim we also need to initialize the other past values like past_clk,
etc. Also to properly initialize them, we need to run a combinational
update step in case any of the wires feeding into the FF are private or
otherwise not part of the FST.
 2022-11-07 14:09:33 +01:00
Claire Xenia Wolf a4eb7e41c0 Add extra time at the end of a sat VCD trace 
Otherwise the final values will not show up in gtkwave waveforms
when looking at the generated traces.

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-11-01 17:51:46 +01:00
Claire Xenia Wolf d04c17fd58 Add miter -cross option 2022-10-24 23:23:33 +02:00
Jannis Harder c77b7343d0 Consistent $mux undef handling 
* Change simlib's $mux cell to use the ternary operator as $_MUX_
  already does
* Stop opt_expr -keepdc from changing S=x to S=0
* Change const eval of $mux and $pmux to match the updated simlib
  (fixes sim)
* The sat behavior of $mux already matches the updated simlib

The verilog frontend uses $mux for the ternary operators and this
changes all interpreations of the $mux cell (that I found) to match the
verilog simulation behavior for the ternary operator. For 'if' and
'case' expressions the frontend may also use $mux but uses $eqx if the
verilog simulation behavior is requested with the '-ifx' option.

For $pmux there is a remaining mismatch between the sat behavior and the
simlib behavior. Resolving this requires more discussion, as the $pmux
cell does not directly correspond to a specific verilog construct.
 2022-10-24 12:03:01 +02:00
Claire Xenia Wolf 0516307637 Add "check -assert" to equiv_opt 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-10-07 16:04:51 +02:00
Claire Xenia Wolf afa5e6bb53 Exclude primary inputs from quiv_make rewiring 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-10-07 16:04:51 +02:00
Claire Xenia Wolf 381ce66f58 Revert "Merge pull request #641 from tklam/master" 
This reverts commit 08be796cb8, reversing
changes made to 38dbb44fa0.

This fixes #2728. PR #641 did not actually "fix" #639.

The actual issue in #639 is not equiv_make, but assumptions in equiv_simple
that are not true for the test case provided in #639.
 2022-10-07 16:04:51 +02:00
Jannis Harder 925f92918a clk2fflogic: Always correctly handle simultaneously changing signals 
This is a complete rewrite of the FF replacing code.

The previous implementation tried to implement the negative hold time by
wrapping async control signals individually with pulse stretching. This
did not correctly model the interaction between different simultaneously
changing inputs (e.g. a falling ALOAD together with a changing AD would
load the changed AD instead of the value AD had when ALOAD was high; a
falling CLR could mask a raising SET for one cycle; etc.).

The new approach first has the logic for all updates using only sampled
values followed by the logic for all updates using only current values.
That way, e.g., a falling ALOAD will load the sampled AD value but a
still active ALOAD will load the current AD value.

The new code also has deterministic behavior for the initial state: no
operation is active when that operation would depend on a specific
previous signal value. This also means clk2fflogic will no longer
generate any additional uninitialized FFs.

I also documented the negative hold time behavior in the help message,
copying the relevant part from async2sync's help messages.
 2022-10-07 16:04:51 +02:00
N. Engelhardt 47e73826e0 mutate: warn if less mutations possible than number requested 2022-10-05 10:59:38 +02:00
Miodrag Milanović fcd1be1422
Merge pull request #3486 from daglem/fix-flowmap-crash 
Fix crash in flowmap
 2022-09-23 16:22:46 +02:00
Kamyar Mohajerani 69787f1906 remove extra space in formating 2022-09-22 15:46:36 +01:00
Kamyar Mohajerani bc1e579483 stat: add tech tech-specific utilizations to json 
- refactor resource util. estimation/calculations for Xilinx and CMOS
 - don't print log_header if "-json" is set
 2022-09-22 15:46:36 +01:00
Dag Lem c4c68e8d86 Fix crash in flowmap 
In 2fcc1ee72e, the following is apparantly added in order to mark any
number of undefined LUT inputs:

lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size()));

However this can only be done if the number of input nodes is less
than minlut.

This fixes #3317
 2022-09-20 14:31:19 +02:00
N. Engelhardt da614fe13a Fix tmpdir naming when passing -nocleanup option to abc(9) on systems where base_tmpdir isn't /tmp/ 2022-09-13 19:30:40 +02:00
N. Engelhardt d829d7fe00
Merge pull request #3458 from QuantamHD/abc_faster 2022-08-31 08:58:42 +02:00
Miodrag Milanovic 4bc1e1d1f1 Makes sure to set initial_top when change, fixes #3462 2022-08-26 17:12:56 +02:00
N. Engelhardt 7d35003c16
Merge pull request #3449 from YosysHQ/aki/show_pathrw 2022-08-25 17:06:29 +02:00
Ethan Mahintorabi 114253cd54 Improves ABC command runtime by 10-100x 
After speaking with the author of ABC he let me know that ifraig is a very old command, and that &get; &fraig -x; &put is over 100x faster than ifraig with improved PPA results.

After making the change I confirmed that this is in fact a major speed up. On our internal designs in O(millions) of standard cells we saw multi hour reductions in runtime.

Also included is an improvement to the dress command. Using AIG based transformations removes the spec it SATs against. Proving the input blif will make sure that no matter what commands are run the dress command can still do its job. I noticed a regression against some LUT mapping jobs that prompted me to fix this.
 2022-08-24 00:35:02 +00:00
KrystalDelusion 9465b2af95 Fitting help messages to 80 character width 
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
 2022-08-24 10:40:57 +12:00
Aki Van Ness 1433a63165
yosys: passes: cmds: show: added filename re-writing to `show -lib` 2022-08-22 06:04:54 -04:00
Jannis Harder f7023d06a2 sim: -hdlname option to preserve flattened hierarchy in sim output 2022-08-16 13:37:30 +02:00
Jannis Harder 4ad13c647e clk2fflogic: Generate less unused logic when using verific 
Verific generates a lot of FFs with an unused async load and we cannot
always optimize that away before running clk2fflogic, so check for that
special case here.
 2022-08-16 13:37:30 +02:00
Jannis Harder 65145db7e7 rename: Add -witness mode 2022-08-16 13:37:30 +02:00
Jannis Harder a2f9ebe43a memory_map: Add -formal option 
This maps memories for a global clock based formal verification flow.
This implies -keepdc, uses $ff cells for ROMs and sets hdlname
attributes.
 2022-08-16 13:37:30 +02:00
Jannis Harder 0cdb14df41 setundef: Do not add anyseq / anyconst to unused memory port clocks 
Instead set those unused clocks to zero.
 2022-08-16 13:37:30 +02:00
Jannis Harder 428ad5b9fd wreduce: Keep more x-bits with -keepdc 2022-08-16 13:37:30 +02:00
Jannis Harder 95db5a9d38 formalff: New -setundef option 
Find FFs with undefined initialization values for which changing the
initialization does not change the observable behavior and initialize
them. For -ff2anyinit, this reduces the number of generated $anyinit
cells that drive wires with private names.
 2022-08-16 13:37:30 +02:00
Jannis Harder a5e1d3b997 formalff: Set new replaced_by_gclk attribute on removed dff's clks 
This attribute can be used by formal backends to indicate which clocks
were mapped to the global clock. Update the btor and smt2 backend which
already handle clock inputs to understand this attribute.
 2022-08-16 13:37:30 +02:00
Jannis Harder c0063288d6 Add the $anyinit cell and the formalff pass 
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
 2022-08-16 13:37:30 +02:00
N. Engelhardt 6f439dc59a
Merge pull request #3425 from YosysHQ/lofty/stat-json 2022-08-11 17:00:54 +02:00
Lofty 59facfa98c stat: add option for machine-readable json output 2022-08-11 13:41:01 +01:00
N. Engelhardt 63fca0dbc2
Merge pull request #3277 from YosysHQ/lofty/rename-scramble_name 2022-08-11 12:06:04 +02:00
Miodrag Milanovic f4a1906721 support file locations containing spaces 2022-08-08 20:30:50 +02:00
Lofty a48dcd1d40 rename: add -scramble-name option to randomly rename selections 2022-08-08 16:03:28 +01:00
Marcelina Kościelnicka f679b756d8 opt_reduce: Fix use-after-free. 
Fixes #3418.
 2022-07-23 17:27:26 +02:00
Jannis Harder 14ba50908b sim: Fix $anyseq in nested modules 2022-07-22 14:48:30 +02:00
Catherine 502b96fe53 Fix external ABC build after commit 0ca0932b5. 2022-07-07 08:38:30 +00:00
Jannis Harder 4a1e54bf70
Merge pull request #3395 from jix/opt_dff_keepdc_initival 
opt_dff: With -keepdc, never turn undef init vals into const drivers
 2022-07-01 16:52:32 +02:00
Jannis Harder 876ef59f4f
Merge pull request #3396 from jix/async2sync_const_clocks 
async2sync: turn FFs with const clks into gclk FFs with feedback
 2022-07-01 16:47:31 +02:00
Jannis Harder 0182b26aba
Merge pull request #3391 from programmerjake/simcheck-allow-smtlib2-blackboxes 
add hierarchy -smtcheck
 2022-07-01 14:38:45 +02:00
Jannis Harder 5db542742b async2sync: turn FFs with const clks into gclk FFs with feedback 
The formal backends do not support multiple clocks. This includes
constant clocks. Constant clocks do appear in what isn't a proper
multiclock design, for example when mapping not fully initialized ROMs.
As converting FFs with constant clocks to FFs using the global is doable
even in a single clock flow, make async2sync do this.
 2022-06-30 12:09:04 +02:00
Jannis Harder a47254bd10 opt_dff: With -keepdc, never turn undef init vals into const drivers 2022-06-29 15:42:39 +02:00
Jannis Harder a6b440b5c9 memory_map: avoid undriven unused FF inputs for -keepdc 2022-06-28 19:05:35 +02:00
Jannis Harder d78d807a7f memory_map: -keepdc option for formal 
Use it when invoking memory_map -rom-only from write_{smt2,btor}.
 2022-06-27 15:47:55 +02:00
George Rennie fbf5d89587 equiv_make: Add -make_assert option 
This adds a -make_assert flag to equiv_make. When used, the pass generates
$eqx and $assert cells to encode equivalence instead of $equiv.
 2022-06-24 00:17:02 +01:00
Jacob Lifshay c16c028831 add hierarchy -smtcheck 
like -simcheck, but allow smtlib2_module modules.
 2022-06-22 20:53:10 -07:00
George Rennie 5dfad5101d chformal: Rename -coverprecond to -coverenable 2022-06-18 18:28:12 +01:00
Jannis Harder e39c422734 chformal: Test -coverprecond and reuse the src attribute 2022-06-18 18:19:26 +01:00
George Rennie c659bd1878 chformal: Add -coverprecond option 
This inserts $cover cells to cover the enable signal (precondition)
for the selected formal cells.
 2022-06-18 18:19:26 +01:00
Marcelina Kościelnicka ab3a9325c3 memory_map: Add -rom-only option. 2022-06-17 16:56:11 +02:00
Marcelina Kościelnicka 01daa077a2 memory_map: Use const drivers instead of FFs for ROMs. 2022-06-17 15:17:14 +02:00
Marcelina Kościelnicka d69091806a memory_libmap: Fix wrprio handling. 2022-06-17 02:09:37 +02:00
Marcelina Kościelnicka 25a4cd7020 memory_libmap: Fix params emitted for unused ports for consistency. 2022-06-16 08:14:08 +02:00
N. Engelhardt 3eaa9e38e0
Merge pull request #3196 from bfg86/bfg86/rename 
Add -suffix option to rename -wire
 2022-06-13 16:00:04 +02:00
Marcelina Kościelnicka 1ff0e1a58a opt_ffinv: Fix use after free. 2022-06-13 14:04:04 +02:00
bfg86 aedd3b7999 Updating help-text with nakengelhardts suggestion. 2022-06-13 09:35:10 +02:00
N. Engelhardt b8ede6162b
Merge pull request #3349 from nakengelhardt/select_count_scratchpad 
Make 'stat' and 'select -count' save counts to scratchpad
 2022-06-09 17:15:02 +02:00
N. Engelhardt 871b277d35
Merge pull request #3359 from jix/fmcombine-memid 
fmcombine: Add _gold/_gate suffix to memids
 2022-06-09 17:12:34 +02:00
Henner Zeller 9d41aa8e28 Avoid unnecessary copy of a potential large constant value. 
The local variable is used just to iterate through the values, so
a const reference is all we need.
 2022-06-09 16:05:51 +01:00
Marcelina Kościelnicka 47efc04a7d wreduce: Introduce -mux_undef option (aligned with opt_expr). 2022-06-08 21:28:58 +02:00
Lofty aae2c01326 sta: warn on unrecognised cells only once 2022-06-08 09:31:49 +01:00
Marcelina Kościelnicka d07828b409 opt_ffinv: Harden against simple ff/inv loop. 2022-06-07 08:20:06 +02:00
Marcelina Kościelnicka 9e8a2ac051 iopadmap: Fix z assignment removal. 
Fixes #3360.
 2022-06-07 04:10:50 +02:00
Jannis Harder 459941c8ff fmcombine: Add _gold/_gate suffix to memids 2022-06-03 21:52:28 +02:00
Miodrag Milanovic d88a5d26b7 Fix preventing show crashing with newer graphviz 2022-06-03 08:38:16 +02:00
Marcelina Kościelnicka 71dfbf33b2 Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. 2022-06-02 23:16:12 +02:00
Marcelina Kościelnicka 3a0aa9c663 memory_dff: Add support for no_rw_check attribute. 2022-06-02 12:49:34 +02:00
N. Engelhardt 61b05051e1 also make 'stat' save counts to scratchpad 2022-06-01 16:01:07 +02:00
N. Engelhardt a55c3db384 have 'select -count' save the count to scratchpad entry 'select.count' 2022-06-01 14:39:33 +02:00
Mohamed A. Bamakhrama 1822be8792 Observe $TMPDIR variable when creating tmp files 
POSIX defines $TMPDIR as containing the pathname of the directory where
programs can create temporary files. On most systems, this variable points to
"/tmp". However, on some systems it can point to a different location.
Without respecting this variable, yosys fails to run on such systems.

Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de>
 2022-05-27 15:06:53 +02:00
gatecat 166a175983 abc9_ops: Don't leave unused derived modules lying around 
These later become accidentally used for techmap replacements for
blackboxes that we don't actually want.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-23 15:02:25 +01:00
Jannis Harder fc65ea47df select: Fix -assert-none and -assert-any error output and docs 
Both of these options consider a selection containing only empty modules
as non-empty. This wasn't mentioned in the documentation nor did the
error message when using `select -assert-none` list those empty modules,
which produced a very confusing error message complaining about a
non-empty selection followed by an empty listing of the selection.

This fixes the documentation and changes the `-assert-none` and
`-assert-any` assertion error messages to also output fully selected
modules (this includes selected empty modules).

It doesn't change the messages for `-assert-count` etc. as they don't
count modules.
 2022-05-19 14:07:34 +02:00
Marcelina Kościelnicka 606f1637ae Add memory_bmux2rom pass. 2022-05-18 22:48:55 +02:00
Marcelina Kościelnicka 7c5dba8b77 Add memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka 9450f308f0 proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
Marcelina Kościelnicka 98c7804b89 opt_ffinv: Use ModIndex instead of ModWalker. 
This avoids using out-of-data index information.
 2022-05-17 02:52:21 +02:00
Marcelina Kościelnicka 2858bb03cd Add opt_ffinv pass. 2022-05-13 23:02:30 +02:00
Marcelina Kościelnicka 990c9b8e11 Add proc_rom pass. 2022-05-13 00:37:14 +02:00
Miodrag Milanović 58b23954e8
Merge pull request #3299 from YosysHQ/mmicko/sim_memory 
sim pass: support for memories
 2022-05-09 09:28:09 +02:00
Marcelina Kościelnicka 77b1dfd8c3 opt_mem: Remove constant-value bit lanes. 2022-05-07 23:13:16 +02:00
imhcyx 71166eeecf memory_share: fix wrong argidx in extra_args 2022-05-05 16:58:39 +08:00
Marcelina Kościelnicka 18a48b1337 abc: Use dict/pool instead of std::map/std::set 2022-05-04 22:04:50 +02:00
Miodrag Milanovic 8e02b3ca30 fix crash when no fst input 2022-05-04 11:21:39 +02:00
Miodrag Milanovic ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Miodrag Milanovic 3730db4b98 AIM file could have gaps in or between inputs and inits 2022-05-02 11:18:30 +02:00
Jannis Harder e0e31bfc5c
Merge pull request #3257 from jix/tribuf-formal 
tribuf: `-formal` option: convert all to logic and detect conflicts
 2022-04-25 16:23:06 +02:00
Miodrag Milanovic bbfdea2f8a Match $anyseq input if connected to public wire 2022-04-22 17:20:17 +02:00
Miodrag Milanovic 4d80bc24c7 Treat $anyseq as input from FST 2022-04-22 16:23:39 +02:00
Miodrag Milanovic 33f4009bb5 Last sample from input does not represent change 2022-04-22 13:46:11 +02:00
Miodrag Milanovic 83cad82b29 latches are always set to zero 2022-04-22 12:04:05 +02:00
Miodrag Milanovic c989adcc2d If not multiclock, output only on clock edges 2022-04-22 12:03:39 +02:00
Miodrag Milanovic 75032a565d Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
Miodrag Milanovic 8fa2f3b260 Fix multiclock for btor2 witness 2022-04-22 11:53:41 +02:00
Miodrag Milanović c3a3f68b4d
Merge pull request #3280 from YosysHQ/micko/fix_readaiw 
Fix reading aiw from other solvers
 2022-04-18 09:49:21 +02:00
Marcelina Kościelnicka 25ff83f0b5 memory_share: Fix up mismatched address widths. 2022-04-15 22:01:00 +02:00
Marcelina Kościelnicka 48eea3efcf opt_dff: Fix behavior on $ff with D == Q. 2022-04-15 22:00:32 +02:00
Miodrag Milanovic 9508bb2330 Fix reading aiw from other solvers 2022-04-15 11:45:16 +02:00
Jannis Harder bc48500548 tribuf: `-formal` option: convert all to logic and detect conflicts 2022-04-12 12:46:22 +02:00
Miodrag Milanovic 868409361c Use wrap_async_control_gate if ff is fine 2022-04-08 16:30:29 +02:00
Iris Johnson ccc6060f52 Makefile: properly conditionalize features requiring compression. 2022-04-07 20:07:44 -05:00
Catherine 8a1d531b25
Merge pull request #3269 from YosysHQ/micko/fix_autotop 
Reorder steps in -auto-top to fix synth command, fixes #3261
 2022-04-07 22:40:35 +00:00
Marcelina Kościelnicka 376d8cb26f abc: Add support for FFs with reset in -dff 2022-04-07 15:05:02 +02:00
Miodrag Milanovic 977002b1d2 Reorder steps in -auto-top to fix synth command, fixes #3261 2022-04-05 14:02:37 +02:00
Marcelina Kościelnicka 0aec79a0da show: Fix width labels. 
See #3266.
 2022-04-04 22:48:09 +02:00
Miodrag Milanovic 6020ba67ac past_ad initial value setting 2022-04-02 19:13:15 +02:00
Miodrag Milanovic 2c96ecc5f7 setInitState can be only one altering values 2022-04-02 19:13:15 +02:00
Miodrag Milanovic b54aecd80a Set past_d value for init state 2022-04-02 19:13:15 +02:00
Jannis Harder 8ca9737180
Merge pull request #3264 from jix/invalid_ff_dcinit_merge 
opt_merge: Add `-keepdc` option required for formal verification
 2022-04-02 12:41:28 +02:00
Jannis Harder ca5b910296 opt_merge: Add `-keepdc` option required for formal verification 
The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.

The keepdc option of `opt` is passed along to `opt_merge` now.
 2022-04-01 21:03:20 +02:00
Miodrag Milanovic 86ce441af6 Set init values for wrapped async control signals 2022-04-01 17:44:00 +02:00
Miodrag Milanovic c95b9b4ba5 Support memories in aiw and multiclock 2022-03-31 13:10:13 +02:00
Lofty c1057cb3e0
Merge pull request #3194 from Ravenslofty/abc9-flow3mfs 
abc9: add flow3mfs script
 2022-03-28 15:51:04 +01:00
gatecat 8b64dc1dce abc9_ops: Also derive blackboxes with timing info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-24 14:36:07 +00:00
Miodrag Milanovic 322ab1cd54 Proper SigBit forming in sim 2022-03-22 14:43:18 +01:00
Miodrag Milanovic ff3b0c2c46 Proper SigBit forming in sim 2022-03-22 14:22:32 +01:00
Miodrag Milanovic 55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanovic 1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic e217e3017a Update sim help message. 2022-03-16 07:55:57 +01:00
Miodrag Milanović 25d6fdfea7
Merge pull request #3232 from YosysHQ/micko/fst2tb 
Added fst2tb pass for generating testbench
 2022-03-14 20:01:55 +01:00
Miodrag Milanovic f5c20b8286 Added fst2tb pass for generating testbench 2022-03-14 19:06:29 +01:00
Claire Xen 5e2992dae2
Merge pull request #3213 from antonblanchard/abc-typo 
abc: Fix {I} and {P} substitution
 2022-03-14 16:05:23 +01:00
Miodrag Milanović cbece4af0c
Merge pull request #3229 from YosysHQ/micko/sim_date 
Add date parameter to enable full date/time and version info
 2022-03-11 19:02:57 +01:00
Claire Xenia Wolf e21badd4b3 Add "sim -q" option 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 16:26:11 +01:00
Miodrag Milanovic 37de369ba7 Add date parameter to enable full date/time and version info 2022-03-11 16:01:59 +01:00
Claire Xenia Wolf be32de1caa Small fix in "sim" help message 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 15:36:23 +01:00
Miodrag Milanovic 5204694123 FstData already do conversion to VCD 2022-03-11 15:21:36 +01:00
Miodrag Milanovic b72c779204 Support cell name in btor witness file 2022-03-11 15:11:14 +01:00
Miodrag Milanovic 357336339a Proper write of memory data 2022-03-11 11:19:53 +01:00
Miodrag Milanovic 295b0d1899 Start work on memory init 2022-03-09 18:34:02 +01:00
Miodrag Milanovic f37ac5d934 Fixes and error check 2022-03-09 09:48:29 +01:00
Miodrag Milanovic ede348cdc2 cleanup 2022-03-07 16:32:32 +01:00
Miodrag Milanovic 1b1ecd4ab0 Error checks for aiger witness 2022-03-07 15:00:14 +01:00
Miodrag Milanovic b6aca1d743 btor2 witness co-simulation 2022-03-07 13:59:36 +01:00
Miodrag Milanović 9581b9adac
Merge pull request #3219 from YosysHQ/micko/quick_vcd 
VCD reader support by using external tool
 2022-03-04 10:42:14 +01:00
Miodrag Milanovic 59983eda17 Add option to ignore X only signals in output 2022-03-02 16:02:13 +01:00
Miodrag Milanovic 48b56a4f7f Write simulation files after simulation is performed 2022-03-02 15:23:07 +01:00
Miodrag Milanovic 28bc88a57e Cleanup 2022-03-02 09:39:22 +01:00
Miodrag Milanovic 94505395a9 Refactor sim output writers 2022-02-28 18:22:39 +01:00
Miodrag Milanovic dfd4c81eac Quick fix 2022-02-28 11:40:06 +01:00
Claire Xenia Wolf 56b968f61c Add writing of aiw files to "sim" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-28 10:50:08 +01:00
Claire Xenia Wolf 1fd3a642c9 Hotfix in AIGER witness reader state machine 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-28 10:41:44 +01:00
Miodrag Milanovic 8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic 9571acc0bf Support extended aiw format 2022-02-27 16:37:40 +01:00
Miodrag Milanovic fca168797e Fix for last clock edge data 2022-02-25 16:15:32 +01:00
Claire Xenia Wolf ca261d3c28 Experimental sim changes 2022-02-25 16:02:06 +01:00
Anton Blanchard 89300b2dca abc: Fix {I} and {P} substitution 
We were searching for {D} after the first match of {I} or {P}.
 2022-02-23 18:54:28 +11:00
Claire Xen a41c1df76f
Merge pull request #3211 from YosysHQ/micko/witness 
Add support for AIGER witness files in "sim" command
 2022-02-22 16:22:06 +01:00
Miodrag Milanovic fd3f08753a Fix handling of ce_over_srst 2022-02-21 16:36:12 +01:00
Claire Xenia Wolf 1aa9ad25d0 Fix cycle 0 in aiger witness co-simulation 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-18 16:27:41 +01:00
Miodrag Milanovic 41754b4207 Added AIGER witness file co simulation 2022-02-18 15:04:02 +01:00
Miodrag Milanovic 13a5c28459 simplify logic of handling flip-flops and latches 2022-02-18 09:17:36 +01:00
Miodrag Milanovic 61752b255f Review cleanup 2022-02-17 17:18:36 +01:00
Miodrag Milanovic fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Claire Xen 49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Claire Xen e016518866
Merge pull request #2019 from boqwxp/glift 
Add `glift` command for creating gate-level information flow tracking models and optimization problems
 2022-02-11 15:51:24 +01:00
bfg86 7ac98d1c87 Add -suffix option to rename -wire. 
See #3195
 2022-02-11 00:05:13 +01:00
Lofty 5ac32ea68c abc9: add flow3mfs script 2022-02-10 18:28:35 +00:00
Miodrag Milanović d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim 
Add co-simulation in sim pass
 2022-02-07 16:36:43 +01:00
Miodrag Milanovic c0a156bcb4 Error detection for co-simulation 2022-02-04 11:11:36 +01:00
Miodrag Milanovic 6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
YRabbit f5609d52c4 Correct a typo in the manual 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-02 21:14:38 +10:00
Miodrag Milanovic 990aee5531 respect hide_internal flag 2022-02-02 10:15:22 +01:00
Miodrag Milanovic 169ffcd2fb unify cycles counting and cleanup 2022-02-02 10:08:23 +01:00
Miodrag Milanovic 820b2fdd65 added stimulus mode and param check 2022-02-02 09:37:32 +01:00
Scott Thibault 0a6e2bd5d5 Update comment 2022-02-02 03:21:09 +01:00
Scott Thibault e04ac4e9e9 Fix unextend method for signed constants 2022-02-02 03:21:09 +01:00
Miodrag Milanovic 8ba2000a50 error when no signal found 2022-01-31 17:41:50 +01:00
Miodrag Milanovic 1b5ff92e62 Cleanup 2022-01-31 13:45:28 +01:00
Miodrag Milanovic eabd0ff115 Compare bits when not all are defined 2022-01-31 13:41:02 +01:00
Miodrag Milanovic 26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic 6513300db7 message update 2022-01-31 11:41:52 +01:00
Miodrag Milanovic 543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic a6959d30df Use edges when explicit 2022-01-31 09:38:25 +01:00
Miodrag Milanovic cbadfa0268 Updating initial state and checks 2022-01-31 09:19:34 +01:00
Miodrag Milanovic 190e44f0da Fix scope 2022-01-31 08:56:29 +01:00
Marcelina Kościelnicka 07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns. 2022-01-30 03:37:52 +01:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Miodrag Milanovic f04d1398e5 check if stop before start 2022-01-28 19:41:43 +01:00
Miodrag Milanovic ecbba625c4 set initial state, only flip-flops 2022-01-28 15:59:13 +01:00
Miodrag Milanovic cb12b7c4d8 ignore not found private signals 2022-01-28 14:20:16 +01:00
Miodrag Milanovic 81b76155d6 recursive check 2022-01-28 13:24:38 +01:00
Miodrag Milanovic 4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic 3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka db33b1e535 opt_dff: Don't mutate muxes while ModWalker is active. 2022-01-28 08:55:56 +01:00
Marcelina Kościelnicka 1759c80a3f memory_bram: Make use of new mem emulation functions to map more RAMs. 2022-01-27 19:31:27 +01:00
Miodrag Milanovic 40018e191b Display values of outputs 2022-01-26 16:52:36 +01:00
Miodrag Milanovic be7be63fec Check if stimulated 2022-01-26 15:51:43 +01:00
Miodrag Milanovic 9a8939f0a4 Read fst and use data to set inputs 2022-01-26 15:50:38 +01:00
Miodrag Milanovic ccfc00705a Add ability to write to FST file 2022-01-26 09:26:19 +01:00
Austin Seipp b022fe61a7 opt_dff: fix sequence point copy paste bug 
Newer GCCs emit the following warning for opt_dff:

    passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
      560 |      ff.has_clk = ff.has_ce = ff.has_clk = false;
          |      ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.

This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2022-01-04 18:18:08 +01:00
Marcelina Kościelnicka f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports. 
Fixes #3117.
 2021-12-20 18:40:14 +01:00
Catherine 4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires. 
Fixes #3113.
 2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Marcelina Kościelnicka 1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka 107aad2cd2 show: Fix wire bit indexing. 
Fixes #3078.
 2021-11-12 15:09:58 +01:00
Claire Xen 4699ddcc1b
Merge pull request #3077 from YosysHQ/claire/genlib 
Add genlib support to ABC command
 2021-11-10 20:02:34 +01:00
Claire Xen c77d5a2aac
Spelling fix in abc.cc 2021-11-10 16:47:54 +01:00
Claire Xenia Wolf 093e287a1e Add genlib support to ABC command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-11-10 16:40:54 +01:00
Marcelina Kościelnicka 506acd52de iopadmap: Fix ebmarassing typo 2021-11-10 14:56:03 +01:00
Marcelina Kościelnicka 15b0d717ed iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
Pepijn de Vos 0c7461fe5e
gowin: widelut support (#3042) 2021-11-06 16:09:30 +01:00
Miodrag Milanovic d5de2a0cdb Make it work on all 2021-11-05 10:51:58 +01:00
Miodrag Milanovic cbb6887ac8 Correct way of setting maybe_unsused on labels 2021-11-05 10:36:15 +01:00
Marcelina Kościelnicka f346868ccc flatten: Keep sigmap around between flatten_cell invocations. 
Fixes #3064.
 2021-11-02 13:18:15 +01:00
Marcelina Kościelnicka 8d881826eb proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka 0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule 
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
 2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka 5cebf6a8ef Change implicit conversions from bool to Sig* to explicit. 
Also fixes some completely broken code in extract_reduce.
 2021-10-21 20:20:31 +02:00
Marcelina Kościelnicka e64456f920 extract_reduce: Refactor and fix input signal construction. 
Fixes #3047.
 2021-10-21 04:10:01 +02:00
Paul Annesley 3efc14f5ad dfflegalize: remove redundant check for initialized dlatch 
This if condition is repeated verbatim, and I can't imagine a legitimate
way the inputs could change in between. I imagine it's a copy/paste
mistake.
 2021-10-17 22:10:37 +02:00
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka ba0723cad7 zinit: Refactor to use FfData. 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka 63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. 
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka f9aad606ca simplemap: refactor to use FfData. 2021-10-02 03:24:57 +02:00
Eddie Hung 96b6410dcb
abc9: make re-entrant (#2993) 
* Add testcase

* Cleanup some state at end of abc9

* Re-assign abc9_box_id from scratch

* Suppress delete unless prep_bypass did something
 2021-09-09 10:06:31 -07:00
Eddie Hung 65316ec926
abc9: holes module to instantiate cells with NEW_ID (#2992) 
* Add testcase

* holes module to instantiate cells with NEW_ID
 2021-09-09 10:06:20 -07:00
Eddie Hung f03e2c30aa
abc9: replace cell type/parameters if derived type already processed (#2991) 
* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
 2021-09-09 10:05:55 -07:00
Marcelina Kościelnicka 9cbff3a4a9 opt_merge: Remove and reinsert init when connecting nets. 
Mutating the SigMap by adding a new connection will throw off FfInitVals
index.  Work around this by removing the relevant init values from index
whenever we connect nets, then re-add the new init value.

Should fix #2920.
 2021-08-22 18:34:11 +02:00
Marcelina Kościelnicka 62d41d4639 opt_clean: Make the init attribute follow the FF's Q. 
Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire.  This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.

Part of another jab at #2920.
 2021-08-22 15:38:29 +02:00
Marcelina Kościelnicka faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits. 
Fixes #2962.
 2021-08-14 15:26:11 +02:00
Marcelina Kościelnicka f791328506 Add opt_mem_widen pass. 
If all of us are wide, then none of us are!
 2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka 1f74ec3535 memory_share: Add -nosat and -nowiden options. 
This unlocks wide port recognition by default.
 2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka 9fdedf4d1c memory_dff: Recognize soft transparency logic. 2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka 616ace2d92 Add new opt_mem_priority pass. 2021-08-13 11:58:52 +02:00
Miodrag Milanović 30927df881
Merge pull request #2932 from YosysHQ/mwk/logger-check-expected 
logger: Add -check-expected subcommand.
 2021-08-13 11:45:20 +02:00
Marcelina Kościelnicka d0d9aca2c3 memory_share: Pass addresses through sigmap_xmux everywhere. 
This fixes wide port recognition in some cases.
 2021-08-13 01:17:55 +02:00
Marcelina Kościelnicka c58ac63c97 logger: Add -check-expected subcommand. 
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
 2021-08-12 17:41:39 +02:00
Marcelina Kościelnicka 72d86c327e memory_dff: Recognize read ports with reset / initial value. 2021-08-11 14:17:48 +02:00
Marcelina Kościelnicka 24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
Marcelina Kościelnicka d25b9088c8 Refactor common parts of SAT-using optimizations into a helper. 
This also aligns the functionality:

- in all cases, the onehot attribute is used to create appropriate
  constraints (previously, opt_dff didn't do it at all, and share
  created one-hot constraints based on $pmux presence alone, which
  is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
  importing the SAT problem (previously only memory_share did this)
  — this avoids creating clauses for hard cells that are unlikely
  to help with proving the UNSATness needed for optimization
 2021-08-09 16:54:35 +02:00
Marcelina Kościelnicka 98003430d6 opt_merge: Use FfInitVals. 
Partial #2920 fix.
 2021-08-08 01:19:22 +02:00
Marcelina Kościelnicka 63f9e0544f memory_share: Don't skip ports with EN wired to input for SAT sharing. 
Fixes #2912.
 2021-08-04 04:47:43 +02:00
Marcelina Kościelnicka 8733e1923a memory_bram: Move init data swizzling before other swizzling. 
Fixes #2907.
 2021-08-03 15:04:10 +02:00
Marcelina Kościelnicka 4451f7f5e9 memory_bram: Some refactoring 
This will make more sense when the new transparency masks land.

Fixes #2902.
 2021-08-01 16:51:24 +02:00
Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards 
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
 2021-07-29 20:55:59 -04:00
Marcelina Kościelnicka 54e75129e5 opt_lut: Allow more than one -dlogic per cell type. 
Fixes #2061.
 2021-07-29 17:30:07 +02:00
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka a0e912ba99 proc: Run opt_expr at the end 2021-07-27 20:44:45 +02:00
Marcelina Kościelnicka 436d42c00c opt_expr: Propagate constants to port connections. 
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value.  This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
 2021-07-27 20:44:26 +02:00
Rupert Swarbrick 7a25246a7e Use new read_id_num helper function elsewhere in hierarchy.cc 2021-07-20 10:13:15 -04:00
Rupert Swarbrick 8fd6b45a3c Extract connection checking logic from expand_module in hierarchy.cc 
No functional change, but pulls more logic out of the expand_module
function.
 2021-07-20 10:13:15 -04:00
Rupert Swarbrick 7d50b83322 Extract missing module support in hierarchy.cc to a helper function 
I think the code is now a bit easier to follow (and has lost some
levels of indentation!).

The only non-trivial change is that I removed the check for
cell->type[0] != '$' when deciding whether to complain if we couldn't
find a module. This will always be true because of the early exit
earlier in the function.
 2021-07-14 22:54:50 -04:00
Rupert Swarbrick 88f20fa4dd Delete unused found_init variable 
Spotted during compilation:

    passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’:
    passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
 2021-07-14 10:19:07 +01:00
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire. 
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
 2021-07-12 00:47:34 +02:00
Rupert Swarbrick e2c9580024 Move interface expansion in hierarchy.cc into a helper class 
There should be no functional change, but this splits up the control
flow across functions, using class fields to hold the state that's
being tracked. The result should be a bit easier to read.

This is part of work to add bind support, but I'm doing some
refactoring in the hierarchy pass to make the code a bit easier to
work with. The idea is that (eventually) the IFExpander object will
hold all the logic for expanding interfaces, and then other code can
do bind insertion.
 2021-06-16 21:48:18 -04:00
gatecat 6a6d049f1c opt_muxtree: Update port_off and port_idx even for constant bits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-11 12:06:35 +01:00
Marcelina Kościelnicka 1667ad658b opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. 
The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
 2021-06-09 19:53:44 +02:00
Marcelina Kościelnicka 12b3a9765d opt_expr: Optimize div/mod by const 1. 
Turns out the code for div by a power of 2 is already almost capable of
optimizing this to a shift-by-0 or and-with-0, which will be further
folded into nothingness; let's beef it up to handle div by 1 as well.

Fixes #2820.
 2021-06-09 17:42:30 +02:00
Claire Xen 55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails 
Fixing old e-mail addresses and deadnames
 2021-06-09 13:22:52 +02:00
Claire Xenia Wolf 588137cd08 Fix deadname SVN links 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:44:37 +02:00
Claire Xenia Wolf 0ada13cbe2 Use HTTPS for website links, gatecat email 
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
 2021-06-09 12:16:56 +02:00
Zachary Snow d9f11bb7a6 autoname: simple perf optimizations 2021-06-08 15:02:42 -04:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka 13b901bf1c memory_map: Improve start_offset handling. 
Fixes #2775.
 2021-05-31 17:45:21 +02:00
Marcelina Kościelnicka 82f5829aba memory_share: Add read port merging. 
This is mostly meant for wide port recognition, but may also happen to
merge some ports with compatible initial/reset values (eg. 0 vs x).
 2021-05-29 16:05:58 +02:00
Marcelina Kościelnicka 2d10caabbc memory_share: Improve sat-based port sharing. 2021-05-28 14:25:33 +02:00
Marcelina Kościelnicka cbf6b719fe Make a few passes auto-call Mem::narrow instead of rejecting wide ports. 
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
 2021-05-28 00:40:56 +02:00
Marcelina Kościelnicka 1eae6025e7 memory_share: Improve same-address merging, recognize wide write ports. 2021-05-27 15:53:12 +02:00
Marcelina Kościelnicka 83a218141c kernel/mem: Add sub_addr helpers. 2021-05-26 03:34:02 +02:00
Marcelina Kościelnicka d99fce3bc7 mem/extract_rdff: Fix "no FF made" edge case. 
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return.  Handle this case correctly in
the helper and in its users.
 2021-05-25 23:42:31 +02:00
Marcelina Kościelnicka 18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 2021-05-25 22:42:03 +02:00
Marcelina Kościelnicka e6b078d156 opt_mem: Add reset/init value support. 2021-05-25 20:06:00 +02:00
Marcelina Kościelnicka 96c7d60304 memory_bram: Respect write port priority. 2021-05-25 16:28:33 +02:00
Marcelina Kościelnicka 5628f5a88f opt_mem_feedback: Respect write port priority. 2021-05-25 15:59:41 +02:00
Marcelina Kościelnicka e0736c1622 Add memory_narrow pass. 2021-05-25 03:04:13 +02:00
Marcelina Kościelnicka 47f958ce45 memory_share: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka 9d5d5a48b1 opt_mem_feedback: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka c1a4730739 memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka 1c903d3e47 sim: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka 69bf5c81c7 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka 835688bf80 opt_mem_feedback: Rewrite feedback path finding logic. 
Fixes #2766.
 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka b706adb809 opt_mem_feedback: Convert to Mem helpers. 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka df2b79ca76 memory_share: Use Mem helpers. 2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka afd5366fc2 extract_rdff: Add initvals parameter. 
This is not used yet, but will be needed when read port reset/initial
value support lands.
 2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka d905990d01 memory_share: Split off feedback path finding as a separate pass. 
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
 2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka 1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff. 
Fixes #1854.
 2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka a23d9409e7 opt_mem: Remove write ports with const-0 EN. 
Fixes #2765.
 2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka 039f4f48d5 memory_memx: Use Mem helper. 2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. 
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
 2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka 8c734e07b8 memory_dff: Use Mem helper. 2021-05-21 02:26:27 +02:00
Marcelina Kościelnicka a6081b46ce connect: Add -assert option, fix non-working sigmap. 
Should be useful for writing tests.
 2021-05-08 15:49:41 +02:00
Marcelina Kościelnicka 5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
whitequark c5c57e3f5e flatten: rewrite memid in memwr actions. 2021-04-09 09:46:53 +00:00
Marcelina Kościelnicka b7ea71e6e3 equiv: Suggest running async2sync or clk2fflogic where appropriate. 
See #2713.
 2021-03-30 18:20:21 +02:00
Eddie Hung 8c5f379435
abc9: uniquify blackboxes like whiteboxes (#2695) 
* abc9_ops: uniquify blackboxes too

* abc9_ops: update comment

* abc9_ops: allow bypass for param-less blackboxes

* Add tests
 2021-03-29 22:02:06 -07:00
Eddie Hung 55dc5a4e4f
abc9: fix SCC issues (#2694) 
* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
 2021-03-29 22:01:57 -07:00
Iris Johnson 4c39189b13
Clarify bugpoint documentation regarding output 
Bugpoint's current documentation does specify that the result of a run is stored as the current design,
however it's easy to skim over what that means in practice. 

Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save
the reduced design.
 2021-03-24 16:24:33 -05:00