mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3395 from jix/opt_dff_keepdc_initival
opt_dff: With -keepdc, never turn undef init vals into const drivers
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commit
4a1e54bf70
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@ -491,12 +491,17 @@ struct OptDffWorker
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ff.has_srst = false;
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ff.sig_d = ff.val_srst;
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changed = true;
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} else {
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} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
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log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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// The D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver).
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ff.has_ce = ff.has_clk = ff.has_srst = false;
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changed = true;
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} else {
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// We need to keep the undefined initival around as such
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ff.sig_d = ff.sig_q;
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ff.has_ce = ff.has_srst = false;
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changed = true;
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}
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} else if (ff.sig_ce == (ff.pol_ce ? State::S1 : State::S0)) {
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// Always-active enable. Just remove it.
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@ -508,13 +513,20 @@ struct OptDffWorker
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}
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}
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if (ff.has_clk) {
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if (ff.sig_clk.is_fully_const()) {
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if (ff.has_clk && ff.sig_clk.is_fully_const()) {
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if (!opt.keepdc || ff.val_init.is_fully_def()) {
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// Const clock — the D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver).
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log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.has_ce = ff.has_clk = ff.has_srst = false;
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changed = true;
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} else {
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// Const clock, but we need to keep the undefined initval around as such
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if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) {
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ff.sig_d = ff.sig_q;
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ff.has_ce = ff.has_srst = false;
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changed = true;
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}
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}
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}
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@ -550,7 +562,7 @@ struct OptDffWorker
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ff.has_srst = false;
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ff.sig_d = ff.val_srst;
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changed = true;
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} else {
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} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
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// The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver).
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log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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@ -567,7 +579,7 @@ struct OptDffWorker
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}
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// The cell has been simplified as much as possible already. Now try to spice it up with enables / sync resets.
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if (ff.has_clk) {
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if (ff.has_clk && ff.sig_d != ff.sig_q) {
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if (!ff.has_arst && !ff.has_sr && (!ff.has_srst || !ff.has_ce || ff.ce_over_srst) && !opt.nosdff) {
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// Try to merge sync resets.
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std::map<ctrls_t, std::vector<int>> groups;
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