riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Reorder steps in -auto-top to fix synth command, fixes #3261

This commit is contained in:
Miodrag Milanovic 2022-04-05 14:02:37 +02:00
parent 957fdb328a
commit 977002b1d2
1 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
passes/hierarchy/hierarchy.cc
View File

@ -976,6 +976,19 @@ struct HierarchyPass : public Pass {
if (mod->get_bool_attribute(ID::top))
top_mod = mod;
if (top_mod == nullptr && auto_top_mode) {
log_header(design, "Finding top of design hierarchy..\n");
dict<Module*, int> db;
for (Module *mod : design->selected_modules()) {
int score = find_top_mod_score(design, mod, db);
log("root of %3d design levels: %-20s\n", score, log_id(mod));
if (!top_mod || score > db[top_mod])
top_mod = mod;
}
if (top_mod != nullptr)
log("Automatically selected %s as design top module.\n", log_id(top_mod));
}
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
IdString top_name = top_mod->name.substr(strlen("$abstract"));
@ -1000,19 +1013,6 @@ struct HierarchyPass : public Pass {
}
}
if (top_mod == nullptr && auto_top_mode) {
log_header(design, "Finding top of design hierarchy..\n");
dict<Module*, int> db;
for (Module *mod : design->selected_modules()) {
int score = find_top_mod_score(design, mod, db);
log("root of %3d design levels: %-20s\n", score, log_id(mod));
if (!top_mod || score > db[top_mod])
top_mod = mod;
}
if (top_mod != nullptr)
log("Automatically selected %s as design top module.\n", log_id(top_mod));
}
if (flag_simcheck && top_mod == nullptr)
log_error("Design has no top module.\n");