mirror of https://github.com/YosysHQ/yosys.git
sim: Internal API to set $initstate
This is not yet added to any of the simulation drivers.
This commit is contained in:
parent
44b26d5c6d
commit
9c6198a827
|
@ -153,6 +153,7 @@ struct SimInstance
|
|||
dict<Cell*, ff_state_t> ff_database;
|
||||
dict<IdString, mem_state_t> mem_database;
|
||||
pool<Cell*> formal_database;
|
||||
pool<Cell*> initstate_database;
|
||||
dict<Cell*, IdString> mem_cells;
|
||||
|
||||
std::vector<Mem> memories;
|
||||
|
@ -256,6 +257,8 @@ struct SimInstance
|
|||
if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
|
||||
formal_database.insert(cell);
|
||||
}
|
||||
if (cell->type == ID($initstate))
|
||||
initstate_database.insert(cell);
|
||||
}
|
||||
|
||||
if (shared->zinit)
|
||||
|
@ -708,6 +711,14 @@ struct SimInstance
|
|||
it.second->update_ph3();
|
||||
}
|
||||
|
||||
void set_initstate_outputs(State state)
|
||||
{
|
||||
for (auto cell : initstate_database)
|
||||
set_state(cell->getPort(ID::Y), state);
|
||||
for (auto child : children)
|
||||
child.second->set_initstate_outputs(state);
|
||||
}
|
||||
|
||||
void writeback(pool<Module*> &wbmods)
|
||||
{
|
||||
if (!ff_database.empty() || !mem_database.empty()) {
|
||||
|
|
Loading…
Reference in New Issue