mirror of https://github.com/YosysHQ/yosys.git
sim: Run a comb-only update step to set past values during FST cosim
The previous approach only initialized past_d and past_ad while for FST cosim we also need to initialize the other past values like past_clk, etc. Also to properly initialize them, we need to run a combinational update step in case any of the wires feeding into the FF are private or otherwise not part of the FST.
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@ -813,18 +813,6 @@ struct SimInstance
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std::string v = shared->fst->valueOf(item.second);
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did_something |= set_state(item.first, Const::from_string(v));
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}
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for (auto &it : ff_database)
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{
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ff_state_t &ff = it.second;
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SigSpec dsig = it.second.data.sig_d;
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Const value = get_state(dsig);
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if (dsig.is_wire()) {
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ff.past_d = value;
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if (ff.data.has_aload)
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ff.past_ad = value;
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did_something |= true;
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}
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}
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for (auto cell : module->cells())
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{
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if (cell->is_mem_cell()) {
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@ -1019,6 +1007,16 @@ struct SimWorker : SimShared
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top->update_ph3();
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}
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void initialize_stable_past()
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{
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if (debug)
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log("\n-- ph1 (initialize) --\n");
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top->update_ph1();
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if (debug)
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log("\n-- ph3 (initialize) --\n");
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top->update_ph3();
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}
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void set_inports(pool<IdString> ports, State value)
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{
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for (auto portname : ports)
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@ -1191,6 +1189,7 @@ struct SimWorker : SimShared
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if (initial) {
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did_something |= top->setInitState();
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initialize_stable_past();
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initial = false;
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}
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if (did_something)
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