mirror of https://github.com/YosysHQ/yosys.git
abc: Add support for FFs with reset in -dff
This commit is contained in:
Marcelina Kościelnicka
parent
4da3f2878b
commit
376d8cb26f
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@ -45,6 +45,7 @@
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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#include "kernel/cost.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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@ -73,6 +74,8 @@ PRIVATE_NAMESPACE_BEGIN
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enum class gate_type_t {
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G_NONE,
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G_FF,
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G_FF0,
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G_FF1,
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G_BUF,
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G_NOT,
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G_AND,
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@ -115,10 +118,11 @@ std::vector<gate_t> signal_list;
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std::map<RTLIL::SigBit, int> signal_map;
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FfInitVals initvals;
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pool<std::string> enabled_gates;
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bool recover_init, cmos_cost;
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bool cmos_cost;
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bool had_init;
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bool clk_polarity, en_polarity;
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RTLIL::SigSpec clk_sig, en_sig;
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bool clk_polarity, en_polarity, arst_polarity, srst_polarity;
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RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
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dict<int, std::string> pi_map, po_map;
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int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
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@ -165,46 +169,84 @@ void mark_port(RTLIL::SigSpec sig)
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void extract_cell(RTLIL::Cell *cell, bool keepff)
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{
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if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
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{
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if (clk_polarity != (cell->type == ID($_DFF_P_)))
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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FfData ff(&initvals, cell);
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gate_type_t type = G(FF);
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if (!ff.has_clk)
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return;
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if (clk_sig != assign_map(cell->getPort(ID::C)))
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if (ff.has_gclk)
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return;
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if (GetSize(en_sig) != 0)
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if (ff.has_aload)
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return;
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goto matching_dff;
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}
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if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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{
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if (clk_polarity != cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)))
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if (ff.has_sr)
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return;
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if (en_polarity != cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
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if (!ff.is_fine)
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return;
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if (clk_sig != assign_map(cell->getPort(ID::C)))
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if (clk_polarity != ff.pol_clk)
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return;
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if (en_sig != assign_map(cell->getPort(ID::E)))
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if (clk_sig != assign_map(ff.sig_clk))
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return;
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goto matching_dff;
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}
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if (0) {
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matching_dff:
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RTLIL::SigSpec sig_d = cell->getPort(ID::D);
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RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
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if (ff.has_ce) {
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if (en_polarity != ff.pol_ce)
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return;
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if (en_sig != assign_map(ff.sig_ce))
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return;
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} else {
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if (GetSize(en_sig) != 0)
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return;
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}
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if (ff.val_init == State::S1) {
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type = G(FF1);
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had_init = true;
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} else if (ff.val_init == State::S0) {
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type = G(FF0);
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had_init = true;
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}
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if (ff.has_arst) {
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if (arst_polarity != ff.pol_arst)
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return;
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if (arst_sig != assign_map(ff.sig_arst))
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return;
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if (ff.val_arst == State::S1) {
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if (type == G(FF0))
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return;
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type = G(FF1);
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} else if (ff.val_arst == State::S0) {
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if (type == G(FF1))
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return;
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type = G(FF0);
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}
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} else {
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if (GetSize(arst_sig) != 0)
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return;
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}
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if (ff.has_srst) {
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if (srst_polarity != ff.pol_srst)
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return;
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if (srst_sig != assign_map(ff.sig_srst))
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return;
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if (ff.val_srst == State::S1) {
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if (type == G(FF0))
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return;
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type = G(FF1);
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} else if (ff.val_srst == State::S0) {
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if (type == G(FF1))
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return;
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type = G(FF0);
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}
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} else {
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if (GetSize(srst_sig) != 0)
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return;
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}
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if (keepff)
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for (auto &c : sig_q.chunks())
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for (auto &c : ff.sig_q.chunks())
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if (c.wire != nullptr)
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c.wire->attributes[ID::keep] = 1;
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assign_map.apply(sig_d);
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assign_map.apply(sig_q);
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map_signal(ff.sig_q, type, map_signal(ff.sig_d));
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map_signal(sig_q, G(FF), map_signal(sig_d));
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module->remove(cell);
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ff.remove();
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return;
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}
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@ -412,7 +454,7 @@ void handle_loops()
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// dot_f = fopen("test.dot", "w");
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for (auto &g : signal_list) {
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if (g.type == G(NONE) || g.type == G(FF)) {
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if (g.type == G(NONE) || g.type == G(FF) || g.type == G(FF0) || g.type == G(FF1)) {
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workpool.insert(g.id);
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} else {
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if (g.in1 >= 0) {
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@ -667,7 +709,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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signal_list.clear();
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pi_map.clear();
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po_map.clear();
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recover_init = false;
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if (clk_str != "$")
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{
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@ -676,20 +717,33 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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en_polarity = true;
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en_sig = RTLIL::SigSpec();
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arst_polarity = true;
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arst_sig = RTLIL::SigSpec();
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srst_polarity = true;
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srst_sig = RTLIL::SigSpec();
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}
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if (!clk_str.empty() && clk_str != "$")
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{
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std::string en_str;
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std::string arst_str;
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std::string srst_str;
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if (clk_str.find(',') != std::string::npos) {
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int pos = clk_str.find(',');
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std::string en_str = clk_str.substr(pos+1);
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en_str = clk_str.substr(pos+1);
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clk_str = clk_str.substr(0, pos);
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if (en_str[0] == '!') {
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en_polarity = false;
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en_str = en_str.substr(1);
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}
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if (module->wire(RTLIL::escape_id(en_str)) != nullptr)
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en_sig = assign_map(module->wire(RTLIL::escape_id(en_str)));
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}
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if (en_str.find(',') != std::string::npos) {
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int pos = en_str.find(',');
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arst_str = en_str.substr(pos+1);
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arst_str = en_str.substr(0, pos);
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}
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if (arst_str.find(',') != std::string::npos) {
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int pos = arst_str.find(',');
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srst_str = arst_str.substr(pos+1);
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srst_str = arst_str.substr(0, pos);
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}
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if (clk_str[0] == '!') {
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clk_polarity = false;
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@ -697,6 +751,30 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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}
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if (module->wire(RTLIL::escape_id(clk_str)) != nullptr)
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clk_sig = assign_map(module->wire(RTLIL::escape_id(clk_str)));
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if (en_str != "") {
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if (en_str[0] == '!') {
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en_polarity = false;
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en_str = en_str.substr(1);
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}
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if (module->wire(RTLIL::escape_id(en_str)) != nullptr)
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en_sig = assign_map(module->wire(RTLIL::escape_id(en_str)));
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}
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if (arst_str != "") {
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if (arst_str[0] == '!') {
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arst_polarity = false;
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arst_str = arst_str.substr(1);
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}
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if (module->wire(RTLIL::escape_id(arst_str)) != nullptr)
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arst_sig = assign_map(module->wire(RTLIL::escape_id(arst_str)));
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}
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if (srst_str != "") {
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if (srst_str[0] == '!') {
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srst_polarity = false;
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srst_str = srst_str.substr(1);
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}
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if (module->wire(RTLIL::escape_id(srst_str)) != nullptr)
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srst_sig = assign_map(module->wire(RTLIL::escape_id(srst_str)));
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}
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}
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if (dff_mode && clk_sig.empty())
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@ -789,10 +867,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
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if (en_sig.size() != 0)
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log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
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if (arst_sig.size() != 0)
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log(", asynchronously reset by %s%s", arst_polarity ? "" : "!", log_signal(arst_sig));
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if (srst_sig.size() != 0)
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log(", synchronously reset by %s%s", srst_polarity ? "" : "!", log_signal(srst_sig));
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log("\n");
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}
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}
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had_init = false;
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for (auto c : cells)
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extract_cell(c, keepff);
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@ -811,6 +894,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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if (en_sig.size() != 0)
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mark_port(en_sig);
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if (arst_sig.size() != 0)
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mark_port(arst_sig);
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if (srst_sig.size() != 0)
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mark_port(srst_sig);
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handle_loops();
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buffer = stringf("%s/input.blif", tempdir_name.c_str());
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@ -917,11 +1006,11 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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fprintf(f, "00-- 1\n");
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fprintf(f, "--00 1\n");
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} else if (si.type == G(FF)) {
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if (si.init == State::S0 || si.init == State::S1) {
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fprintf(f, ".latch ys__n%d ys__n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
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recover_init = true;
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} else
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fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id);
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fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id);
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} else if (si.type == G(FF0)) {
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fprintf(f, ".latch ys__n%d ys__n%d 0\n", si.in1, si.id);
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} else if (si.type == G(FF1)) {
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fprintf(f, ".latch ys__n%d ys__n%d 1\n", si.in1, si.id);
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} else if (si.type != G(NONE))
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log_abort();
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if (si.type != G(NONE))
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@ -1043,6 +1132,9 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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design->select(module, wire);
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}
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SigMap mapped_sigmap(mapped_mod);
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FfInitVals mapped_initvals(&mapped_sigmap, mapped_mod);
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std::map<std::string, int> cell_stats;
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for (auto c : mapped_mod->cells())
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{
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@ -1149,20 +1241,41 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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}
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if (c->type == ID(DFF)) {
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log_assert(clk_sig.size() == 1);
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RTLIL::Cell *cell;
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if (en_sig.size() == 0) {
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cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
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} else {
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FfData ff(module, &initvals, remap_name(c->name));
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ff.width = 1;
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ff.is_fine = true;
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ff.has_clk = true;
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ff.pol_clk = clk_polarity;
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ff.sig_clk = clk_sig;
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if (en_sig.size() != 0) {
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log_assert(en_sig.size() == 1);
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cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
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cell->setPort(ID::E, en_sig);
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ff.has_ce = true;
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ff.pol_ce = en_polarity;
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ff.sig_ce = en_sig;
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}
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RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
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if (had_init)
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ff.val_init = init;
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else
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ff.val_init = State::Sx;
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if (arst_sig.size() != 0) {
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log_assert(arst_sig.size() == 1);
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ff.has_arst = true;
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ff.pol_arst = arst_polarity;
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ff.sig_arst = arst_sig;
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ff.val_arst = init;
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}
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if (srst_sig.size() != 0) {
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log_assert(srst_sig.size() == 1);
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ff.has_srst = true;
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ff.pol_srst = srst_polarity;
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ff.sig_srst = srst_sig;
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ff.val_srst = init;
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}
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ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
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ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
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RTLIL::Cell *cell = ff.emit();
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if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
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for (auto name : {ID::D, ID::Q}) {
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RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
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cell->setPort(name, module->wire(remapped_name));
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}
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cell->setPort(ID::C, clk_sig);
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design->select(module, cell);
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continue;
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}
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@ -1180,20 +1293,38 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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if (c->type == ID(_dff_)) {
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log_assert(clk_sig.size() == 1);
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RTLIL::Cell *cell;
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if (en_sig.size() == 0) {
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cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
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} else {
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FfData ff(module, &initvals, remap_name(c->name));
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ff.width = 1;
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ff.is_fine = true;
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ff.has_clk = true;
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ff.pol_clk = clk_polarity;
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ff.sig_clk = clk_sig;
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if (en_sig.size() != 0) {
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log_assert(en_sig.size() == 1);
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cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
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cell->setPort(ID::E, en_sig);
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ff.pol_ce = en_polarity;
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ff.sig_ce = en_sig;
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}
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RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
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if (had_init)
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ff.val_init = init;
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else
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ff.val_init = State::Sx;
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if (arst_sig.size() != 0) {
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log_assert(arst_sig.size() == 1);
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ff.pol_arst = arst_polarity;
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ff.sig_arst = arst_sig;
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ff.val_arst = init;
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}
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if (srst_sig.size() != 0) {
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log_assert(srst_sig.size() == 1);
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ff.pol_srst = srst_polarity;
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ff.sig_srst = srst_sig;
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ff.val_srst = init;
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}
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ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
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ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
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RTLIL::Cell *cell = ff.emit();
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if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
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for (auto name : {ID::D, ID::Q}) {
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RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
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cell->setPort(name, module->wire(remapped_name));
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}
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cell->setPort(ID::C, clk_sig);
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design->select(module, cell);
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continue;
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}
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@ -1229,15 +1360,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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module->connect(conn);
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}
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||||
|
||||
if (recover_init)
|
||||
for (auto wire : mapped_mod->wires()) {
|
||||
if (wire->attributes.count(ID::init)) {
|
||||
Wire *w = module->wire(remap_name(wire->name));
|
||||
log_assert(w->attributes.count(ID::init) == 0);
|
||||
w->attributes[ID::init] = wire->attributes.at(ID::init);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &it : cell_stats)
|
||||
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
|
||||
int in_wires = 0, out_wires = 0;
|
||||
|
|
@ -1884,7 +2006,7 @@ struct AbcPass : public Pass {
|
|||
std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
|
||||
std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
|
||||
|
||||
typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
|
||||
typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec, bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
|
||||
std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
|
||||
std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
|
||||
|
||||
|
|
@ -1912,20 +2034,31 @@ struct AbcPass : public Pass {
|
|||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
|
||||
{
|
||||
key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID::C)), true, RTLIL::SigSpec());
|
||||
}
|
||||
else
|
||||
if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
|
||||
{
|
||||
bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
|
||||
bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
|
||||
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID::C)), this_en_pol, assign_map(cell->getPort(ID::E)));
|
||||
}
|
||||
else
|
||||
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
|
||||
continue;
|
||||
|
||||
FfData ff(&initvals, cell);
|
||||
if (!ff.has_clk)
|
||||
continue;
|
||||
if (ff.has_gclk)
|
||||
continue;
|
||||
if (ff.has_aload)
|
||||
continue;
|
||||
if (ff.has_sr)
|
||||
continue;
|
||||
if (!ff.is_fine)
|
||||
continue;
|
||||
key = clkdomain_t(
|
||||
ff.pol_clk,
|
||||
ff.sig_clk,
|
||||
ff.has_ce ? ff.pol_ce : true,
|
||||
ff.has_ce ? assign_map(ff.sig_ce) : RTLIL::SigSpec(),
|
||||
ff.has_arst ? ff.pol_arst : true,
|
||||
ff.has_arst ? assign_map(ff.sig_arst) : RTLIL::SigSpec(),
|
||||
ff.has_srst ? ff.pol_srst : true,
|
||||
ff.has_srst ? assign_map(ff.sig_srst) : RTLIL::SigSpec()
|
||||
);
|
||||
|
||||
unassigned_cells.erase(cell);
|
||||
expand_queue.insert(cell);
|
||||
expand_queue_up.insert(cell);
|
||||
|
|
@ -1998,7 +2131,7 @@ struct AbcPass : public Pass {
|
|||
expand_queue.swap(next_expand_queue);
|
||||
}
|
||||
|
||||
clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
|
||||
clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec(), true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
|
||||
for (auto cell : unassigned_cells) {
|
||||
assigned_cells[key].push_back(cell);
|
||||
assigned_cells_reverse[cell] = key;
|
||||
|
|
@ -2006,15 +2139,21 @@ struct AbcPass : public Pass {
|
|||
|
||||
log_header(design, "Summary of detected clock domains:\n");
|
||||
for (auto &it : assigned_cells)
|
||||
log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
|
||||
log(" %d cells in clk=%s%s, en=%s%s, arst=%s%s, srst=%s%s\n", GetSize(it.second),
|
||||
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
|
||||
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
|
||||
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)),
|
||||
std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)),
|
||||
std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first)));
|
||||
|
||||
for (auto &it : assigned_cells) {
|
||||
clk_polarity = std::get<0>(it.first);
|
||||
clk_sig = assign_map(std::get<1>(it.first));
|
||||
en_polarity = std::get<2>(it.first);
|
||||
en_sig = assign_map(std::get<3>(it.first));
|
||||
arst_polarity = std::get<4>(it.first);
|
||||
arst_sig = assign_map(std::get<5>(it.first));
|
||||
srst_polarity = std::get<6>(it.first);
|
||||
srst_sig = assign_map(std::get<7>(it.first));
|
||||
abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
|
||||
keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
|
||||
assign_map.set(mod);
|
||||
|
|
|
|||
Loading…
Reference in New Issue