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Revert "Merge pull request #641 from tklam/master" 

This reverts commit 08be796cb8, reversing
changes made to 38dbb44fa0.

This fixes #2728. PR #641 did not actually "fix" #639.

The actual issue in #639 is not equiv_make, but assumptions in equiv_simple
that are not true for the test case provided in #639.
This commit is contained in:
Claire Xenia Wolf 2021-04-28 16:52:04 +02:00 committed by Jannis Harder
parent 925f92918a
commit 381ce66f58
1 changed files with 5 additions and 81 deletions
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86
passes/equiv/equiv_make.cc
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@ -40,16 +40,6 @@ struct EquivMakeWorker
pool<SigBit> undriven_bits;
SigMap assign_map;
dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells
CellTypes comb_ct;
EquivMakeWorker()
{
comb_ct.setup_internals();
comb_ct.setup_stdcells();
}
void read_blacklists()
{
for (auto fn : blacklists)
@ -288,31 +278,16 @@ struct EquivMakeWorker
}
}
init_bit2driven();
pool<Cell*> visited_cells;
for (auto c : cells_list)
for (auto &conn : c->connections())
if (!ct.cell_output(c->type, conn.first)) {
SigSpec old_sig = assign_map(conn.second);
SigSpec new_sig = rd_signal_map(old_sig);
if(old_sig != new_sig) {
SigSpec tmp_sig = old_sig;
for (int i = 0; i < GetSize(old_sig); i++) {
SigBit old_bit = old_sig[i], new_bit = new_sig[i];
visited_cells.clear();
if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
continue;
log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type),
log_signal(old_bit), log_signal(new_bit));
tmp_sig[i] = new_bit;
}
c->setPort(conn.first, tmp_sig);
if (old_sig != new_sig) {
log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type),
log_signal(old_sig), log_signal(new_sig));
c->setPort(conn.first, new_sig);
}
}
@ -403,57 +378,6 @@ struct EquivMakeWorker
}
}
void init_bit2driven()
{
for (auto cell : equiv_mod->cells()) {
if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
continue;
for (auto &conn : cell->connections())
{
if (yosys_celltypes.cell_input(cell->type, conn.first))
for (auto bit : assign_map(conn.second))
{
bit2driven[bit].insert(cell);
}
}
}
}
bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
{
if (source_bit == target_bit)
return true;
if (bit2driven.count(source_bit) == 0)
return false;
auto driven_cells = bit2driven.at(source_bit);
for (auto driven_cell: driven_cells)
{
bool is_comb = comb_ct.cell_known(driven_cell->type);
if (!is_comb)
continue;
if (visited_cells.count(driven_cell) > 0)
continue;
visited_cells.insert(driven_cell);
for (auto &conn: driven_cell->connections())
{
if (yosys_celltypes.cell_input(driven_cell->type, conn.first))
continue;
for (auto bit: conn.second) {
bool is_in_fanout = check_signal_in_fanout(visited_cells, bit, target_bit);
if (is_in_fanout == true)
return true;
}
}
}
return false;
}
void run()
{
copy_to_equiv();