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Merge branch 'YosysHQ:master' into main/issue2525

This commit is contained in:
Muthiah Annamalai (முத்து அண்ணாமலை) 2023-05-16 21:21:32 -07:00 committed by GitHub
parent 665e0f6131 acfdc5cc42
commit 693c609eec
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GPG Key ID: 4AEE18F83AFDEB23
18 changed files with 2505 additions and 57 deletions
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15
CHANGELOG
View File

@ -2,9 +2,22 @@
List of major changes and improvements between releases
=======================================================
Yosys 0.28 .. Yosys 0.28-dev
Yosys 0.29 .. Yosys 0.29-dev
--------------------------
Yosys 0.28 .. Yosys 0.29
--------------------------
* New commands and options
- Added "synthprop" pass for synthesizable properties.
* Verific support
- Handle conditions on clocked concurrent assertions in unclocked
procedural contexts.
* Verilog
- Fix const eval of unbased unsized constants.
- Handling of attributes for struct / union variables.
Yosys 0.27 .. Yosys 0.28
--------------------------
* Verilog

4
Makefile
View File

@ -141,7 +141,7 @@ LDLIBS += -lrt
endif
endif
YOSYS_VER := 0.28+12
YOSYS_VER := 0.29+11
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
@ -157,7 +157,7 @@ endif
OBJS = kernel/version_$(GIT_REV).o
bumpversion:
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0d6f4b0.. | wc -l`/;" Makefile
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9c5a60e.. | wc -l`/;" Makefile
# set 'ABCREV = default' to use abc/ as it is
#

22
frontends/verific/verific.cc
View File

@ -2011,6 +2011,28 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
Instance *inst = net->Driver();
// Detect condition expression in sva_at_only mode
if (sva_at_only)
do {
Instance *inst_mux = net->Driver();
if (inst_mux->Type() != PRIM_MUX)
break;
bool pwr1 = inst_mux->GetInput1()->IsPwr();
bool pwr2 = inst_mux->GetInput2()->IsPwr();
if (!pwr1 && !pwr2)
break;
Net *sva_net = pwr1 ? inst_mux->GetInput2() : inst_mux->GetInput1();
if (!verific_is_sva_net(importer, sva_net))
break;
inst = sva_net->Driver();
cond_net = inst_mux->GetControl();
cond_pol = pwr1;
} while (0);
if (inst != nullptr && inst->Type() == PRIM_SVA_AT)
{
net = inst->GetInput1();

17
frontends/verific/verificsva.cc
View File

@ -1598,12 +1598,17 @@ struct VerificSvaImporter
if (inst == nullptr)
{
log_assert(trig == State::S1);
if (accept_p != nullptr)
*accept_p = importer->net_map_at(net);
if (reject_p != nullptr)
*reject_p = module->Not(NEW_ID, importer->net_map_at(net));
if (trig != State::S1) {
if (accept_p != nullptr)
*accept_p = module->And(NEW_ID, trig, importer->net_map_at(net));
if (reject_p != nullptr)
*reject_p = module->And(NEW_ID, trig, module->Not(NEW_ID, importer->net_map_at(net)));
} else {
if (accept_p != nullptr)
*accept_p = importer->net_map_at(net);
if (reject_p != nullptr)
*reject_p = module->Not(NEW_ID, importer->net_map_at(net));
}
}
else
if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||

83
passes/cmds/plugin.cc
View File

@ -41,50 +41,70 @@ std::map<std::string, std::string> loaded_plugin_aliases;
void load_plugin(std::string filename, std::vector<std::string> aliases)
{
std::string orig_filename = filename;
rewrite_filename(filename);
if (filename.find('/') == std::string::npos)
// Would something like this better be put in `rewrite_filename`?
if (filename.find("/") == std::string::npos)
filename = "./" + filename;
#ifdef WITH_PYTHON
if (!loaded_plugins.count(filename) && !loaded_python_plugins.count(filename)) {
const bool is_loaded = loaded_plugins.count(orig_filename) && loaded_python_plugins.count(orig_filename);
#else
if (!loaded_plugins.count(filename)) {
const bool is_loaded = loaded_plugins.count(orig_filename);
#endif
#ifdef WITH_PYTHON
boost::filesystem::path full_path(filename);
if(strcmp(full_path.extension().c_str(), ".py") == 0)
if (!is_loaded) {
// Check if we're loading a python script
if(filename.find(".py") != std::string::npos)
{
std::string path(full_path.parent_path().c_str());
filename = full_path.filename().c_str();
filename = filename.substr(0,filename.size()-3);
PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str());
PyErr_Print();
PyObject *module_p = PyImport_ImportModule(filename.c_str());
if(module_p == NULL)
{
#ifdef WITH_PYTHON
boost::filesystem::path full_path(filename);
std::string path(full_path.parent_path().c_str());
filename = full_path.filename().c_str();
filename = filename.substr(0,filename.size()-3);
PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str());
PyErr_Print();
log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str());
return;
}
loaded_python_plugins[orig_filename] = module_p;
Pass::init_register();
PyObject *module_p = PyImport_ImportModule(filename.c_str());
if(module_p == NULL)
{
PyErr_Print();
log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str());
return;
}
loaded_python_plugins[orig_filename] = module_p;
Pass::init_register();
#else
log_error(
"\n This version of Yosys cannot load python plugins.\n"
" Ensure Yosys is built with Python support to do so.\n"
);
#endif
} else {
#endif
// Otherwise we assume it's a native plugin
void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL);
if (hdl == NULL && orig_filename.find('/') == std::string::npos)
hdl = dlopen((proc_share_dirname() + "plugins/" + orig_filename + ".so").c_str(), RTLD_LAZY|RTLD_LOCAL);
if (hdl == NULL)
log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror());
loaded_plugins[orig_filename] = hdl;
Pass::init_register();
void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL);
// We were unable to open the file, try to do so from the plugin directory
if (hdl == NULL && orig_filename.find('/') == std::string::npos) {
hdl = dlopen([orig_filename]() {
std::string new_path = proc_share_dirname() + "plugins/" + orig_filename;
// Check if we need to append .so
if (new_path.find(".so") == std::string::npos)
new_path.append(".so");
return new_path;
}().c_str(), RTLD_LAZY|RTLD_LOCAL);
}
if (hdl == NULL)
log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror());
loaded_plugins[orig_filename] = hdl;
Pass::init_register();
#ifdef WITH_PYTHON
}
#endif
}
for (auto &alias : aliases)
@ -182,4 +202,3 @@ struct PluginPass : public Pass {
} PluginPass;
YOSYS_NAMESPACE_END

8
passes/cmds/rename.cc
View File

@ -116,6 +116,8 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
}
cache.emplace(module, -1);
std::vector<std::pair<Cell *, IdString>> renames;
bool has_witness_signals = false;
for (auto cell : module->cells())
{
@ -130,8 +132,9 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
c = '_';
auto new_id = module->uniquify("\\_witness_." + name);
cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
module->rename(cell, new_id);
renames.emplace_back(cell, new_id);
}
break;
}
if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) {
@ -155,6 +158,9 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
}
}
}
for (auto rename : renames) {
module->rename(rename.first, rename.second);
}
cache[module] = has_witness_signals;
return has_witness_signals;

1
passes/sat/Makefile.inc
View File

@ -19,3 +19,4 @@ OBJS += passes/sat/fminit.o
ifeq ($(DISABLE_SPAWN),0)
OBJS += passes/sat/qbfsat.o
endif
OBJS += passes/sat/synthprop.o

15
passes/sat/sim.cc
View File

@ -1162,6 +1162,11 @@ struct SimWorker : SimShared
}
for(auto& writer : outputfiles)
writer->write(use_signal);
if (writeback) {
pool<Module*> wbmods;
top->writeback(wbmods);
}
}
void update(bool gclk)
@ -1265,11 +1270,6 @@ struct SimWorker : SimShared
register_output_step(10*numcycles + 2);
write_output_files();
if (writeback) {
pool<Module*> wbmods;
top->writeback(wbmods);
}
}
void run_cosim_fst(Module *topmod, int numcycles)
@ -1394,11 +1394,6 @@ struct SimWorker : SimShared
}
write_output_files();
if (writeback) {
pool<Module*> wbmods;
top->writeback(wbmods);
}
delete fst;
}

269
passes/sat/synthprop.cc Normal file
View File

@ -0,0 +1,269 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2023 Miodrag Milanovic <micko@yosyshq.com>
* Copyright (C) 2023
* National Technology & Engineering Solutions of Sandia, LLC (NTESS)
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
YOSYS_NAMESPACE_BEGIN
struct TrackingItem
{
pool<Cell*> assertion_cells;
std::vector<std::string> names;
};
typedef dict<RTLIL::Module*, TrackingItem> TrackingData;
struct SynthPropWorker
{
// pointer to main design
RTLIL::Design *design;
RTLIL::IdString top_name;
RTLIL::Module *module;
std::string map_file;
bool or_outputs;
IdString port_name;
IdString reset_name;
bool reset_pol;
// basic contrcutor
SynthPropWorker(RTLIL::Design *design) : design(design), or_outputs(false), port_name(RTLIL::escape_id("assertions")) {}
void tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path);
void run();
};
void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path)
{
log("%*sTracing in module %s..\n", 2*depth, "", log_id(mod));
tracing_data[mod] = TrackingItem();
int cnt = 0;
for (auto cell : mod->cells()) {
if (cell->type == ID($assert)) {
log("%*sFound assert %s..\n", 2*(depth+1), "", log_id(cell));
tracing_data[mod].assertion_cells.emplace(cell);
if (!or_outputs) {
tracing_data[mod].names.push_back(hier_path + "." + log_id(cell));
}
cnt++;
}
else if (RTLIL::Module *submod = design->module(cell->type)) {
tracing(submod, depth+1, tracing_data, hier_path + "." + log_id(cell));
if (!or_outputs) {
for (size_t i = 0; i < tracing_data[submod].names.size(); i++)
tracing_data[mod].names.push_back(tracing_data[submod].names[i]);
} else {
cnt += tracing_data[submod].names.size();
}
}
}
if (or_outputs && (cnt > 0)) {
tracing_data[mod].names.push_back("merged_asserts");
}
}
void SynthPropWorker::run()
{
if (!module->get_bool_attribute(ID::top))
log_error("Module is not TOP module\n");
TrackingData tracing_data;
tracing(module, 0, tracing_data, log_id(module->name));
for (auto &data : tracing_data) {
if (data.second.names.size() == 0) continue;
RTLIL::Wire *wire = data.first->addWire(port_name, data.second.names.size());
wire->port_output = true;
data.first->fixup_ports();
}
RTLIL::Wire *output = nullptr;
for (auto &data : tracing_data) {
int num = 0;
RTLIL::Wire *port_wire = data.first->wire(port_name);
if (!reset_name.empty() && data.first == module) {
port_wire = data.first->addWire(NEW_ID, data.second.names.size());
output = port_wire;
}
pool<Wire*> connected;
for (auto cell : data.second.assertion_cells) {
if (cell->type == ID($assert)) {
RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID);
RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire);
data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire);
if (!or_outputs) {
data.first->connect(SigBit(port_wire,num), result_wire);
} else {
connected.emplace(result_wire);
}
num++;
}
}
for (auto cell : data.first->cells()) {
if (RTLIL::Module *submod = design->module(cell->type)) {
if (tracing_data[submod].names.size() > 0) {
if (!or_outputs) {
cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size()));
} else {
RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
cell->setPort(port_name, result_wire);
connected.emplace(result_wire);
}
num += tracing_data[submod].names.size();
}
}
}
if (or_outputs && connected.size() > 0) {
RTLIL::Wire *prev_wire = nullptr;
for (auto wire : connected ) {
if (!prev_wire) {
prev_wire = wire;
} else {
RTLIL::Wire *result = data.first->addWire(NEW_ID);
data.first->addOr(NEW_ID, prev_wire, wire, result);
prev_wire = result;
}
}
data.first->connect(port_wire, prev_wire);
}
}
// If no assertions found
if (tracing_data[module].names.size() == 0) return;
if (!reset_name.empty()) {
int width = tracing_data[module].names.size();
SigSpec reset = module->wire(reset_name);
reset.extend_u0(width, true);
module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol);
}
if (!map_file.empty()) {
std::ofstream fout;
fout.open(map_file, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", map_file.c_str());
for (auto name : tracing_data[module].names) {
fout << name << std::endl;
}
}
}
struct SyntProperties : public Pass {
SyntProperties() : Pass("synthprop", "synthesize SVA properties") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synthprop [options]\n");
log("\n");
log("This creates synthesizable properties for selected module.\n");
log("\n");
log("\n");
log(" -name <portname>\n");
log("\n");
log("Name output port for assertions (default: assertions).\n");
log("\n");
log("\n");
log(" -map <filename>\n");
log("\n");
log("Write port mapping for synthesizable properties.\n");
log("\n");
log("\n");
log(" -or_outputs\n");
log("\n");
log("Or all outputs together to create a single output that goes high when any\n");
log("property is violated, instead of generating individual output bits.\n");
log("\n");
log("\n");
log(" -reset <portname>\n");
log("\n");
log("Name of top-level reset input. Latch a high state on the generated outputs\n");
log("until an asynchronous top-level reset input is activated.\n");
log("\n");
log("\n");
log(" -resetn <portname>\n");
log("\n");
log("Name of top-level reset input (inverse polarity). Latch a high state on the\n");
log("generated outputs until an asynchronous top-level reset input is activated.\n");
log("\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design* design)
{
log_header(design, "Executing SYNTHPROP pass.\n");
SynthPropWorker worker(design);
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-name" && argidx+1 < args.size()) {
worker.port_name = RTLIL::escape_id(args[++argidx]);
continue;
}
if (args[argidx] == "-map" && argidx+1 < args.size()) {
worker.map_file = args[++argidx];
continue;
}
if (args[argidx] == "-reset" && argidx+1 < args.size()) {
worker.reset_name = RTLIL::escape_id(args[++argidx]);
worker.reset_pol = true;
continue;
}
if (args[argidx] == "-resetn" && argidx+1 < args.size()) {
worker.reset_name = RTLIL::escape_id(args[++argidx]);
worker.reset_pol = false;
continue;
}
if (args[argidx] == "-or_outputs") {
worker.or_outputs = true;
continue;
}
break;
}
if (args.size() != argidx)
cmd_error(args, argidx, "Extra argument.");
auto *top = design->top_module();
if (top == nullptr)
log_cmd_error("Can't find top module in current design!\n");
auto *reset = top->wire(worker.reset_name);
if (!worker.reset_name.empty() && reset == nullptr)
log_cmd_error("Can't find reset line in current design!\n");
worker.module = top;
worker.run();
}
} SyntProperties;
YOSYS_NAMESPACE_END

8
passes/techmap/libparse.cc
View File

@ -236,10 +236,10 @@ LibertyAst *LibertyParser::parse()
if (tok == ':' && ast->value.empty()) {
tok = lexer(ast->value);
if (tok != 'v')
error();
tok = lexer(str);
while (tok == '+' || tok == '-' || tok == '*' || tok == '/') {
if (tok == 'v') {
tok = lexer(str);
}
while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') {
ast->value += tok;
tok = lexer(str);
if (tok != 'v')

1
techlibs/gowin/Makefile.inc
View File

@ -3,6 +3,7 @@ OBJS += techlibs/gowin/synth_gowin.o
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))

2
techlibs/gowin/arith_map.v
View File

@ -62,6 +62,6 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
.SUM(Y[i])
);
end endgenerate
assign X = AA ^ BB;
assign X = AA ^ BB ^ {Y_WIDTH{BI}};
endmodule

76
techlibs/gowin/cells_xtra.py Normal file
View File

@ -0,0 +1,76 @@
#!/usr/bin/env python3
# Base on Nexus cells_xtra.py
from argparse import ArgumentParser
import os.path
from enum import Enum, auto
import sys
import re
class State(Enum):
OUTSIDE = auto()
IN_MODULE = auto()
IN_PARAMETER = auto()
_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',
'IDES16', 'IDES4', 'IDES8', 'IOBUF', 'IVIDEO', 'LUT1', 'LUT2',
'LUT3', 'LUT4', 'MUX2', 'MUX2_LUT5', 'MUX2_LUT6', 'MUX2_LUT7',
'MUX2_LUT8', 'OBUF', 'ODDR', 'ODDRC', 'OSC', 'OSCF', 'OSCH',
'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4',
'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4',
'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC'
}
def xtract_cells_decl(dir, fout):
fname = os.path.join(dir, 'prim_sim.v')
with open(fname) as f:
state = State.OUTSIDE
for l in f:
l, _, comment = l.partition('//')
if l.startswith("module "):
cell_name = l[7:l.find('(')].strip()
if cell_name not in _skip:
state = State.IN_MODULE
fout.write(f'\nmodule {cell_name} (...);\n')
elif l.startswith(('input', 'output', 'inout')) and state == State.IN_MODULE:
fout.write(l)
if l[-1] != '\n':
fout.write('\n')
elif l.startswith('parameter') and state == State.IN_MODULE:
fout.write(l)
if l.rstrip()[-1] == ',':
state = State.IN_PARAMETER
if l[-1] != '\n':
fout.write('\n')
elif state == State.IN_PARAMETER:
fout.write(l)
if l.rstrip()[-1] == ';':
state = State.IN_MODULE
if l[-1] != '\n':
fout.write('\n')
elif l.startswith('endmodule') and state == State.IN_MODULE:
state = State.OUTSIDE
fout.write('endmodule\n')
if l[-1] != '\n':
fout.write('\n')
if __name__ == '__main__':
parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.')
parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/')
args = parser.parse_args()
dirs = [
os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'),
]
with open('cells_xtra.v', 'w') as fout:
fout.write('// Created by cells_xtra.py\n')
fout.write('\n')
for dir in dirs:
if not os.path.isdir(dir):
print(f'{dir} is not a directory')
xtract_cells_decl(dir, fout)

2003
techlibs/gowin/cells_xtra.v Normal file
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File diff suppressed because it is too large Load Diff

1
techlibs/gowin/synth_gowin.cc
View File

@ -207,6 +207,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -specify -lib +/gowin/cells_sim.v");
run("read_verilog -specify -lib +/gowin/cells_xtra.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}

20
tests/arch/gowin/compare.v Normal file
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@ -0,0 +1,20 @@
module top
(
input [4:0] x,
input [4:0] y,
output lt,
output le,
output gt,
output ge,
output eq,
output ne
);
assign lt = x < y;
assign le = x <= y;
assign gt = x > y;
assign ge = x >= y;
assign eq = x == y;
assign ne = x != y;
endmodule

9
tests/arch/gowin/compare.ys Normal file
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@ -0,0 +1,9 @@
read_verilog compare.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 5 t:ALU

8
tests/liberty/issue3498_bad.lib Executable file
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library(fake) {
cell(bugbad) {
bundle(X) {
members(x1, x2);
power_down_function : !a+b ;
}
}
}