mirror of https://github.com/YosysHQ/yosys.git
support file locations containing spaces
This commit is contained in:
Miodrag Milanovic
parent
6c65ca4e50
commit
f4a1906721
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@ -216,7 +216,7 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt,
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QbfSolutionType ret;
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const std::string yosys_smtbmc_exe = proc_self_dirname() + "yosys-smtbmc";
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const std::string smtbmc_warning = "z3: WARNING:";
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const std::string smtbmc_cmd = stringf("%s -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1",
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const std::string smtbmc_cmd = stringf("\"%s\" -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1",
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yosys_smtbmc_exe.c_str(), opt.get_solver_name().c_str(),
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(opt.timeout != 0? stringf("--timeout %d", opt.timeout) : "").c_str(),
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(opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file : "").c_str(),
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@ -789,15 +789,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
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module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
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std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
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std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str());
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if (!liberty_files.empty() || !genlib_files.empty()) {
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for (std::string liberty_file : liberty_files)
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abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
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abc_script += stringf("read_lib -w \"%s\"; ", liberty_file.c_str());
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for (std::string liberty_file : genlib_files)
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abc_script += stringf("read_library %s; ", liberty_file.c_str());
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abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str());
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if (!constr_file.empty())
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abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
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abc_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str());
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} else
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if (!lut_costs.empty())
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abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
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@ -1085,7 +1085,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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fclose(f);
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}
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buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
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buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
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log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
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#ifndef YOSYS_LINK_ABC
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@ -175,12 +175,12 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
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if (!lut_costs.empty())
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abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
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else if (!lut_file.empty())
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abc9_script += stringf("read_lut %s; ", lut_file.c_str());
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abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str());
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else
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log_abort();
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log_assert(!box_file.empty());
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abc9_script += stringf("read_box %s; ", box_file.c_str());
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abc9_script += stringf("read_box \"%s\"; ", box_file.c_str());
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abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
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if (!script_file.empty()) {
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@ -264,7 +264,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
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fclose(f);
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}
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buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
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buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
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log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
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#ifndef YOSYS_LINK_ABC
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@ -1,4 +1,5 @@
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*.log
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*.json
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/run-test.mk
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+*_synth.v
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+*_testbench
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@ -17,7 +17,7 @@ generate_target() {
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generate_ys_test() {
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ys_file=$1
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yosys_args=${2:-}
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generate_target "$ys_file" "$YOSYS_BASEDIR/yosys -ql ${ys_file%.*}.log $yosys_args $ys_file"
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generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args $ys_file"
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}
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# $ generate_bash_test bash_file
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@ -1,6 +1,6 @@
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#!/usr/bin/env bash
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libs=""
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libs=()
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genvcd=false
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use_xsim=false
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use_modelsim=false
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@ -15,7 +15,7 @@ xinclude_opts=""
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minclude_opts=""
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scriptfiles=""
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scriptopt=""
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toolsdir="$(cd $(dirname $0); pwd)"
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toolsdir="$(cd "$(dirname "$0")"; pwd)"
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warn_iverilog_git=false
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# The following are used in verilog to firrtl regression tests.
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# Typically these will be passed as environment variables:
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@ -25,8 +25,8 @@ firrtl2verilog=""
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xfirrtl="../xfirrtl"
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abcprog="$toolsdir/../../yosys-abc"
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if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
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( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
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if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then
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( set -ex; ${CC:-gcc} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1
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fi
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while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
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@ -38,7 +38,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
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G)
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warn_iverilog_git=true ;;
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l)
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libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
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libs+=("$(cd "$(dirname "$OPTARG")"; pwd)/$(basename "$OPTARG")");;
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w)
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genvcd=true ;;
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k)
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@ -162,7 +162,7 @@ do
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cp ../${bn}_tb.v ${bn}_tb.v
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fi
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if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
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compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} $libs \
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compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \
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"$toolsdir"/../../techlibs/common/simlib.v \
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"$toolsdir"/../../techlibs/common/simcells.v
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if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
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@ -171,11 +171,11 @@ do
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test_passes() {
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"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
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compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
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${bn}_tb.v ${bn}_syn${test_count}.v $libs \
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${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
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"$toolsdir"/../../techlibs/common/simlib.v \
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"$toolsdir"/../../techlibs/common/simcells.v
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if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
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$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
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"$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count}
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test_count=$(( test_count + 1 ))
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}
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