mirror of https://github.com/YosysHQ/yosys.git
simplemap: Map `$xnor` to `$_XNOR_` cells
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell.
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@ -61,25 +61,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
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if (cell->type == ID($xnor))
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_t[i]);
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gate->setPort(ID::Y, sig_y[i]);
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}
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sig_y = sig_t;
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}
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IdString gate_type;
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if (cell->type == ID($and)) gate_type = ID($_AND_);
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if (cell->type == ID($or)) gate_type = ID($_OR_);
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if (cell->type == ID($xor)) gate_type = ID($_XOR_);
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if (cell->type == ID($xnor)) gate_type = ID($_XOR_);
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if (cell->type == ID($xnor)) gate_type = ID($_XNOR_);
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log_assert(!gate_type.empty());
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for (int i = 0; i < GetSize(sig_y); i++) {
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@ -32,7 +32,7 @@ select -assert-count 1 c:*
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cd fine_keepdc
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simplemap
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opt_expr -keepdc
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select -assert-count 1 t:$_XOR_
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select -assert-count 1 t:$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
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@ -22,9 +22,8 @@ simplemap
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equiv_opt -assert opt_expr
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design -load postopt
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select -assert-none t:$_XOR_
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select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
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select -assert-count 3 t:$_NOT_
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select -assert-none t:$_XNOR_
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select -assert-count 2 t:$_NOT_
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design -reset
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read_verilog -icells <<EOT
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@ -36,7 +35,7 @@ EOT
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select -assert-count 2 t:$_XNOR_
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equiv_opt -assert opt_expr
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design -load postopt
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select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
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select -assert-none t:$_XNOR_
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select -assert-count 1 t:$_NOT_
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