mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3391 from programmerjake/simcheck-allow-smtlib2-blackboxes
add hierarchy -smtcheck
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commit
0182b26aba
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@ -2379,6 +2379,9 @@ resolves positional module parameters, unrolls array instances, and more.
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like -check, but also throw an error if blackbox modules are
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instantiated, and throw an error if the design has no top module.
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-smtcheck
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like -simcheck, but allow smtlib2_module modules.
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-purge_lib
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by default the hierarchy command will not remove library (blackbox)
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modules. use this option to also remove unused blackbox modules.
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@ -439,7 +439,8 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
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}
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}
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bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, bool flag_simcheck, std::vector<std::string> &libdirs)
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bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, bool flag_simcheck, bool flag_smtcheck,
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std::vector<std::string> &libdirs)
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{
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bool did_something = false;
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std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
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@ -477,7 +478,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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RTLIL::Module *mod = design->module(cell->type);
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if (!mod)
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{
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mod = get_module(*design, *cell, *module, flag_check || flag_simcheck, libdirs);
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mod = get_module(*design, *cell, *module, flag_check || flag_simcheck || flag_smtcheck, libdirs);
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// If we still don't have a module, treat the cell as a black box and skip
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// it. Otherwise, we either loaded or derived something so should set the
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@ -495,11 +496,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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// interfaces.
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if_expander.visit_connections(*cell, *mod);
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if (flag_check || flag_simcheck)
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if (flag_check || flag_simcheck || flag_smtcheck)
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check_cell_connections(*module, *cell, *mod);
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if (mod->get_blackbox_attribute()) {
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if (flag_simcheck)
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if (flag_simcheck || (flag_smtcheck && !mod->get_bool_attribute(ID::smtlib2_module)))
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log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n",
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cell->type.c_str(), module->name.c_str(), cell->name.c_str());
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continue;
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@ -737,6 +738,9 @@ struct HierarchyPass : public Pass {
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log(" like -check, but also throw an error if blackbox modules are\n");
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log(" instantiated, and throw an error if the design has no top module.\n");
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log("\n");
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log(" -smtcheck\n");
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log(" like -simcheck, but allow smtlib2_module modules.\n");
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log("\n");
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log(" -purge_lib\n");
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log(" by default the hierarchy command will not remove library (blackbox)\n");
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log(" modules. use this option to also remove unused blackbox modules.\n");
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@ -803,6 +807,7 @@ struct HierarchyPass : public Pass {
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bool flag_check = false;
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bool flag_simcheck = false;
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bool flag_smtcheck = false;
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bool purge_lib = false;
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RTLIL::Module *top_mod = NULL;
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std::string load_top_mod;
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@ -821,7 +826,7 @@ struct HierarchyPass : public Pass {
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-generate" && !flag_check && !flag_simcheck && !top_mod) {
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if (args[argidx] == "-generate" && !flag_check && !flag_simcheck && !flag_smtcheck && !top_mod) {
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generate_mode = true;
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log("Entering generate mode.\n");
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while (++argidx < args.size()) {
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@ -868,6 +873,10 @@ struct HierarchyPass : public Pass {
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flag_simcheck = true;
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continue;
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}
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if (args[argidx] == "-smtcheck") {
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flag_smtcheck = true;
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continue;
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}
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if (args[argidx] == "-purge_lib") {
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purge_lib = true;
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continue;
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@ -1013,7 +1022,7 @@ struct HierarchyPass : public Pass {
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}
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}
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if (flag_simcheck && top_mod == nullptr)
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if ((flag_simcheck || flag_smtcheck) && top_mod == nullptr)
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log_error("Design has no top module.\n");
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if (top_mod != NULL) {
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@ -1039,7 +1048,7 @@ struct HierarchyPass : public Pass {
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}
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for (auto module : used_modules) {
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if (expand_module(design, module, flag_check, flag_simcheck, libdirs))
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if (expand_module(design, module, flag_check, flag_simcheck, flag_smtcheck, libdirs))
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did_something = true;
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}
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