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chformal: Test -coverprecond and reuse the src attribute
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@ -273,8 +273,8 @@ struct ChformalPass : public Pass {
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if (mode =='p')
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{
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for (auto cell : constr_cells)
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module->addCover(NEW_ID, cell->getPort(ID::EN), State::S1,
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"$auto$coverprecond$" + cell->get_src_attribute());
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module->addCover(NEW_ID_SUFFIX("coverprecond"),
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cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
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}
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else
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if (mode == 'c')
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@ -0,0 +1,25 @@
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read_verilog -formal <<EOT
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module top(input a, b, c, d);
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always @* begin
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if (a) assert (b == c);
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if (!a) assert (b != c);
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if (b) assume (c);
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if (c) cover (d);
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end
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endmodule
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EOT
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prep -top top
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select -assert-count 1 t:$cover
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chformal -cover -coverprecond
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select -assert-count 2 t:$cover
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chformal -assert -coverprecond
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select -assert-count 4 t:$cover
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chformal -assume -coverprecond
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select -assert-count 5 t:$cover
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