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sim: Run level triggered async updates to fixpoint during initialization

This commit is contained in:
Jannis Harder 2023-05-25 12:46:16 +02:00
parent 52c8c28d2c
commit 7caeb922a0
1 changed files with 21 additions and 7 deletions
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28
passes/sat/sim.cc
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@ -589,7 +589,7 @@ struct SimInstance
}
}
bool update_ph2(bool gclk)
bool update_ph2(bool gclk, bool stable_past_update = false)
{
bool did_something = false;
@ -600,7 +600,7 @@ struct SimInstance
Const current_q = get_state(ff.data.sig_q);
if (ff_data.has_clk) {
if (ff_data.has_clk && !stable_past_update) {
// flip-flops
State current_clk = get_state(ff_data.sig_clk)[0];
if (ff_data.pol_clk ? (ff.past_clk == State::S0 && current_clk != State::S0) :
@ -621,7 +621,7 @@ struct SimInstance
if (ff_data.has_aload) {
State current_aload = get_state(ff_data.sig_aload)[0];
if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
current_q = ff_data.has_clk ? ff.past_ad : get_state(ff.data.sig_ad);
current_q = ff_data.has_clk && !stable_past_update ? ff.past_ad : get_state(ff.data.sig_ad);
}
}
// async reset
@ -672,6 +672,8 @@ struct SimInstance
}
else
{
if (stable_past_update)
continue;
if (port.clk_polarity ?
(mdb.past_wr_clk[port_idx] == State::S1 || get_state(port.clk) != State::S1) :
(mdb.past_wr_clk[port_idx] == State::S0 || get_state(port.clk) != State::S0))
@ -701,7 +703,7 @@ struct SimInstance
}
for (auto it : children)
if (it.second->update_ph2(gclk)) {
if (it.second->update_ph2(gclk, stable_past_update)) {
dirty_children.insert(it.second);
did_something = true;
}
@ -1197,9 +1199,21 @@ struct SimWorker : SimShared
void initialize_stable_past()
{
if (debug)
log("\n-- ph1 (initialize) --\n");
top->update_ph1();
while (1)
{
if (debug)
log("\n-- ph1 (initialize) --\n");
top->update_ph1();
if (debug)
log("\n-- ph2 (initialize) --\n");
if (!top->update_ph2(false, true))
break;
}
if (debug)
log("\n-- ph3 (initialize) --\n");
top->update_ph3(true);