ABC9: Cell Port Bug Patch (#3670)

* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>

backends/aiger/xaiger.cc

@@ -274,6 +274,10 @@ struct XAigerWriter
 						continue;
 					auto offset = i.first.offset;
 
+					auto rhs = cell->getPort(i.first.name);
+					if (offset >= rhs.size())
+						continue;
+
 #ifndef NDEBUG
 					if (ys_debug(1)) {
 						static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
@@ -281,7 +285,7 @@ struct XAigerWriter
 								log_id(cell->type), log_id(i.first.name), offset, d);
 					}
 #endif
-					arrival_times[cell->getPort(i.first.name)[offset]] = d;
+					arrival_times[rhs[offset]] = d;
 				}
 
 				if (abc9_flop)

passes/techmap/abc9_ops.cc

@@ -674,8 +674,12 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 				continue;
 
 			auto offset = i.first.offset;
-			auto O = module->addWire(NEW_ID);
+			if (!cell->hasPort(i.first.name))
+				continue;
 			auto rhs = cell->getPort(i.first.name);
+			if (offset >= rhs.size())
+				continue;
+			auto O = module->addWire(NEW_ID);
 
 #ifndef NDEBUG
 			if (ys_debug(1)) {

tests/arch/xilinx/bug3670.v

@@ -0,0 +1,13 @@
+module bug3670(input we, output [31:0] o1, o2, output o3);
+    // Completely missing port connections, where first affected port
+    // (ADDRARDADDR) has a $setup delay
+    RAMB36E1 ram1(.DOADO(o1));
+
+    // Under-specified input port connections (WEA is 4 bits) which
+    // has a $setup delay
+    RAMB36E1 ram2(.WEA(we), .DOADO(o2));
+
+    // Under-specified output port connections (DOADO is 32 bits)
+    // with clk-to-q delay
+    RAMB36E1 ram3(.DOADO(o3));
+endmodule

tests/arch/xilinx/bug3670.ys

@@ -0,0 +1,3 @@
+read_verilog bug3670.v
+read_verilog -lib -specify +/xilinx/cells_sim.v
+abc9