mirror of https://github.com/YosysHQ/yosys.git
opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells
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@ -1527,6 +1527,31 @@ skip_identity:
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goto next_cell; \
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} \
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}
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#define FOLD_2ARG_SIMPLE_CELL(_t, B_ID) \
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if (cell->type == ID($##_t)) { \
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RTLIL::SigSpec a = cell->getPort(ID::A); \
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RTLIL::SigSpec b = cell->getPort(B_ID); \
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assign_map.apply(a), assign_map.apply(b); \
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if (a.is_fully_const() && b.is_fully_const()) { \
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RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const())); \
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cover("opt.opt_expr.const.$" #_t); \
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replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \
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goto next_cell; \
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} \
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}
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#define FOLD_MUX_CELL(_t) \
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if (cell->type == ID($##_t)) { \
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RTLIL::SigSpec a = cell->getPort(ID::A); \
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RTLIL::SigSpec b = cell->getPort(ID::B); \
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RTLIL::SigSpec s = cell->getPort(ID::S); \
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assign_map.apply(a), assign_map.apply(b), assign_map.apply(s); \
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if (a.is_fully_const() && b.is_fully_const() && s.is_fully_const()) { \
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RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), s.as_const())); \
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cover("opt.opt_expr.const.$" #_t); \
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replace_cell(assign_map, module, cell, stringf("%s, %s, %s", log_signal(a), log_signal(b), log_signal(s)), ID::Y, y); \
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goto next_cell; \
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} \
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}
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FOLD_1ARG_CELL(not)
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FOLD_2ARG_CELL(and)
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@ -1558,6 +1583,9 @@ skip_identity:
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FOLD_2ARG_CELL(gt)
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FOLD_2ARG_CELL(ge)
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FOLD_2ARG_CELL(eqx)
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FOLD_2ARG_CELL(nex)
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FOLD_2ARG_CELL(add)
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FOLD_2ARG_CELL(sub)
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FOLD_2ARG_CELL(mul)
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@ -1570,6 +1598,11 @@ skip_identity:
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FOLD_1ARG_CELL(pos)
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FOLD_1ARG_CELL(neg)
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FOLD_MUX_CELL(mux);
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FOLD_MUX_CELL(pmux);
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FOLD_2ARG_SIMPLE_CELL(bmux, ID::S);
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FOLD_2ARG_SIMPLE_CELL(demux, ID::S);
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// be very conservative with optimizing $mux cells as we do not want to break mux trees
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if (cell->type == ID($mux)) {
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RTLIL::SigSpec input = assign_map(cell->getPort(ID::S));
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