mirror of https://github.com/YosysHQ/yosys.git
wreduce: Keep more x-bits with -keepdc
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95db5a9d38
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@ -166,8 +166,8 @@ struct WreduceWorker
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for (int i = GetSize(sig_q)-1; i >= 0; i--)
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{
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if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) &&
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(!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) {
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if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || (!config->keepdc && initval[i] == State::Sx)) &&
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(!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || (!config->keepdc && rst_value[i] == State::Sx))) {
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module->connect(sig_q[i], State::S0);
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initvals.remove_init(sig_q[i]);
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sig_d.remove(i);
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@ -175,8 +175,8 @@ struct WreduceWorker
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continue;
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}
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if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] &&
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(!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) {
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if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] && (!config->keepdc || initval[i] != State::Sx) &&
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(!has_reset || i >= GetSize(rst_value) || (rst_value[i] == rst_value[i-1] && (!config->keepdc || rst_value[i] != State::Sx)))) {
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module->connect(sig_q[i], sig_q[i-1]);
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initvals.remove_init(sig_q[i]);
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sig_d.remove(i);
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