mirror of https://github.com/YosysHQ/yosys.git
Match $anyseq input if connected to public wire
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4d80bc24c7
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@ -809,13 +809,19 @@ struct SimInstance
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($anyseq))) {
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SigSpec sig_y= cell->getPort(ID::Y);
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SigSpec sig_y = sigmap(cell->getPort(ID::Y));
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if (sig_y.is_wire()) {
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Wire *wire = sig_y.as_wire();
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fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
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if (id==0)
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
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inputs[wire] = id;
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bool found = false;
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for(auto &item : fst_handles) {
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if (item.second==0) continue; // Ignore signals not found
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if (sig_y == sigmap(item.first)) {
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inputs[sig_y.as_wire()] = item.second;
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found = true;
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break;
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}
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}
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if (!found)
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str());
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}
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}
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}
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