mirror of https://github.com/YosysHQ/yosys.git
stat: add tech tech-specific utilizations to json
- refactor resource util. estimation/calculations for Xilinx and CMOS - don't print log_header if "-json" is set
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@ -149,6 +149,78 @@ struct statdata_t
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}
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}
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unsigned int estimate_xilinx_lc()
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{
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unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
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unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
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unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
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unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
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unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
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unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
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unsigned int lc_cnt = 0;
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lc_cnt += lut6_cnt;
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lc_cnt += lut5_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut5_cnt, lut1_cnt);
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lut5_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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lc_cnt += lut4_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut4_cnt, lut1_cnt);
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lut4_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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if (lut2_cnt) {
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int cnt = std::min(lut4_cnt, lut2_cnt);
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lut4_cnt -= cnt;
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lut2_cnt -= cnt;
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}
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lc_cnt += lut3_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut3_cnt, lut1_cnt);
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lut3_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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if (lut2_cnt) {
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int cnt = std::min(lut3_cnt, lut2_cnt);
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lut3_cnt -= cnt;
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lut2_cnt -= cnt;
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}
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if (lut3_cnt) {
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int cnt = (lut3_cnt + 1) / 2;
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lut3_cnt -= cnt;
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}
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lc_cnt += (lut2_cnt + lut1_cnt + 1) / 2;
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return lc_cnt;
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}
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unsigned int cmos_transistor_count(bool *tran_cnt_exact)
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{
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unsigned int tran_cnt = 0;
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auto &gate_costs = CellCosts::cmos_gate_cost();
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for (auto it : num_cells_by_type) {
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auto ctype = it.first;
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auto cnum = it.second;
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if (gate_costs.count(ctype))
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tran_cnt += cnum * gate_costs.at(ctype);
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else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
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tran_cnt += cnum * 16;
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else
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*tran_cnt_exact = false;
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}
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return tran_cnt;
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}
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void log_data(RTLIL::IdString mod_name, bool top_mod)
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{
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log(" Number of wires: %6u\n", num_wires);
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@ -176,74 +248,14 @@ struct statdata_t
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if (tech == "xilinx")
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{
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unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
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unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
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unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
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unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
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unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
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unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
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unsigned int lc_cnt = 0;
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lc_cnt += lut6_cnt;
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lc_cnt += lut5_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut5_cnt, lut1_cnt);
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lut5_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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lc_cnt += lut4_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut4_cnt, lut1_cnt);
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lut4_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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if (lut2_cnt) {
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int cnt = std::min(lut4_cnt, lut2_cnt);
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lut4_cnt -= cnt;
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lut2_cnt -= cnt;
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}
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lc_cnt += lut3_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut3_cnt, lut1_cnt);
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lut3_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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if (lut2_cnt) {
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int cnt = std::min(lut3_cnt, lut2_cnt);
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lut3_cnt -= cnt;
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lut2_cnt -= cnt;
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}
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if (lut3_cnt) {
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int cnt = (lut3_cnt + 1) / 2;
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lut3_cnt -= cnt;
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}
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lc_cnt += (lut2_cnt + lut1_cnt + 1) / 2;
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log("\n");
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log(" Estimated number of LCs: %10u\n", lc_cnt);
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log(" Estimated number of LCs: %10u\n", estimate_xilinx_lc());
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}
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if (tech == "cmos")
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{
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unsigned int tran_cnt = 0;
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bool tran_cnt_exact = true;
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auto &gate_costs = CellCosts::cmos_gate_cost();
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for (auto it : num_cells_by_type) {
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auto ctype = it.first;
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auto cnum = it.second;
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if (gate_costs.count(ctype))
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tran_cnt += cnum * gate_costs.at(ctype);
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else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
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tran_cnt += cnum * 16;
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else
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tran_cnt_exact = false;
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}
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unsigned int tran_cnt = cmos_transistor_count(&tran_cnt_exact);
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log("\n");
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log(" Estimated number of transistors: %10u%s\n", tran_cnt, tran_cnt_exact ? "" : "+");
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@ -273,7 +285,20 @@ struct statdata_t
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first_line = false;
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}
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log("\n");
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log(" }\n");
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log(" }");
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if (tech == "xilinx")
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{
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log(",\n");
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log(" \"estimated_num_lc\": %10u", estimate_xilinx_lc());
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}
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if (tech == "cmos")
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{
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bool tran_cnt_exact = true;
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unsigned int tran_cnt = cmos_transistor_count(&tran_cnt_exact);
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log(",\n");
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log(" \"estimated_num_transistors\": \"%10u%s\"", tran_cnt, tran_cnt_exact ? "" : "+");
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}
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log("\n");
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log(" }");
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}
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};
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@ -352,8 +377,6 @@ struct StatPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Printing statistics.\n");
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bool width_mode = false, json_mode = false;
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RTLIL::Module *top_mod = nullptr;
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std::map<RTLIL::IdString, statdata_t> mod_stat;
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@ -391,6 +414,9 @@ struct StatPass : public Pass {
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}
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extra_args(args, argidx, design);
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if(!json_mode)
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log_header(design, "Printing statistics.\n");
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if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode)
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log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
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