Commit Graph

700 Commits

Author SHA1 Message Date
tangxifan 66e5e141a1 improve fabric key loader to reduce runtime 2020-07-07 10:19:34 -06:00
tangxifan 824b56f14c fabric key can now accept instance name only; decoders are no longer part of the key 2020-07-06 16:42:33 -06:00
tangxifan 462fc0d04e add spice transistor wrapper writer 2020-07-05 14:50:29 -06:00
tangxifan b38ee0e8be add spice writer functions 2020-07-05 13:58:05 -06:00
tangxifan 81171a8f97 start transplanting FPGA-SPICE 2020-07-05 12:10:12 -06:00
tangxifan 1ad6e8292a move constants from verilog domain to common so that FPGA-SPICE can share 2020-07-05 11:39:46 -06:00
tangxifan 7c2a0a6ad2 streamline fabric verilog options 2020-07-05 11:28:14 -06:00
tangxifan 83e26adf90 add module usage types for future FPGA-SPICE development 2020-07-04 22:33:54 -06:00
tangxifan 4f8260a7ba remove obselete codes and update regression tests 2020-07-04 17:31:34 -06:00
tangxifan 033c92c365 precisely reserve memory for child blocks in bitstream manager 2020-07-03 22:47:21 -06:00
tangxifan 46f038c829 bug fix in grid config block allocation 2020-07-03 20:46:04 -06:00
tangxifan f040fc78a9 now reserve blocks in bitstream manager can accurately capture the size 2020-07-03 20:06:12 -06:00
tangxifan 8067a13346 bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream 2020-07-03 15:56:20 -06:00
tangxifan 2a9377b3f4 use encoded address in storage of fabric bitstream to save memory 2020-07-03 15:12:29 -06:00
tangxifan 1f38e17111 bug fix for naming conflicts in mux local encoder and architecture decoders 2020-07-03 14:12:13 -06:00
tangxifan 70d9678578 reserve child block in bistream manager 2020-07-03 14:04:10 -06:00
tangxifan 2783fda344 use index range instead of vector for block bitstream 2020-07-03 11:42:38 -06:00
tangxifan 6ea857ae6c use fast method to inquire number of bits and blocks in bitstream databases 2020-07-03 10:55:25 -06:00
tangxifan 7ca1a5bdc1 Fabric bitstream now allocates vectors in conditions for memory efficiency 2020-07-03 10:17:03 -06:00
tangxifan 8a45e48a1c minor fix 2020-07-02 22:27:48 -06:00
tangxifan 246b4d5ac6 reserve block bits to save memory 2020-07-02 21:52:32 -06:00
tangxifan dee4be96af reserve all the input/output net storage in bitstream manager 2020-07-02 19:17:34 -06:00
tangxifan f97e3bfba6 add timer to openfpga shell 2020-07-02 18:02:33 -06:00
tangxifan 81c9fcb7c0 bug fix when optimizing the fabric bitstream data structure 2020-07-02 16:41:32 -06:00
tangxifan adee87569d enable fast bitstream building by creating a frame view of fabric 2020-07-02 16:25:36 -06:00
tangxifan 9608cefa86 remove id vector in fabric bitstream database and replace with more memory efficient implementation 2020-07-02 16:08:50 -06:00
tangxifan 9f19c36a89 use char in fabric bitstream to save memory footprint 2020-07-02 15:56:50 -06:00
tangxifan 405824081b reserve configuration blocks and bits in bitstream manager builder to be memory efficient 2020-07-02 15:28:52 -06:00
tangxifan b85af57971 optimizing fabric bitsteream memory footprint 2020-07-02 12:39:18 -06:00
tangxifan ac22ba28e4 add config protocol type information to simulation ini file 2020-07-02 12:26:59 -06:00
tangxifan 81ecfa3197 add comments to clarify how to select CB ports when connecting to SBs at the top level 2020-07-01 14:44:40 -06:00
tangxifan 0a3c746fb1 now split CB module bus ports into lower/upper parts 2020-07-01 14:37:13 -06:00
tangxifan cb2baed257 bug fix in simulation ini GPIO width 2020-07-01 13:39:12 -06:00
tangxifan b74dde919d add additional information in the simulation ini file for UVM 2020-07-01 13:07:39 -06:00
tangxifan e688ca1388 update fabric bitstream writer to support various configuration protocols 2020-07-01 11:54:28 -06:00
tangxifan 1015880d0e use easy-to-access net look up in switch block module builder 2020-06-30 18:15:41 -06:00
tangxifan 05187f8aa4 use typedef to short the module pin information 2020-06-30 18:07:22 -06:00
tangxifan 2e7684b746 adapt bus ports in connection block module builder 2020-06-30 17:50:53 -06:00
tangxifan 2ef083c49d adapt SB module builder to use bus ports 2020-06-30 16:02:40 -06:00
tangxifan f023652ac4 keep optimizing memory footprint of module manager by using net terminal storage 2020-06-30 14:18:05 -06:00
tangxifan f49cabeeda optimize memory efficiency for module net id storage 2020-06-30 11:33:06 -06:00
tangxifan 23bcad0678 use more robust net builder in inter tile connections 2020-06-30 10:49:17 -06:00
tangxifan 025d4a3599 use efficient net builder in top module connection builder 2020-06-29 23:28:26 -06:00
tangxifan e7d5736269 add profile time to top module builder for better spot on runtime/memory overhead sources 2020-06-29 23:17:03 -06:00
tangxifan 57e6c84252 add reserve net sources and sinks to module manager 2020-06-29 22:49:11 -06:00
tangxifan 66746f69da optimizing memory efficiency by reserving nets in module manager 2020-06-29 21:27:43 -06:00
tangxifan e9937954f2 optimizing the constant writing in Verilog for single bits 2020-06-29 12:29:25 -06:00
tangxifan 9d32a5b81f add alias name support for fabric key 2020-06-27 14:59:53 -06:00
tangxifan ebf5636e7b add verbose output to edge sorting for GSBs 2020-06-26 17:10:51 -06:00
tangxifan aded675633 rename files in fpga bitstream library to be consistent with conventions 2020-06-21 13:06:39 -06:00
tangxifan d526f08782 deploy bitstream reader in openfpga shell 2020-06-20 18:48:19 -06:00
tangxifan 675a59ecb8 Move fpga_bitstream to the libopenfpga library and add XML reader 2020-06-20 18:25:17 -06:00
tangxifan 5d79a3f69f critical bug fixed when annotating the routing results.
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
tangxifan 4f7e8020a8 minor fix on the format of arch bitstream writer 2020-06-17 00:08:28 -06:00
tangxifan b91c30191a add input and output net echo in arch bitstream database 2020-06-17 00:04:55 -06:00
tangxifan 19c0b57df6 ignore invalid nets when decoding bitstream 2020-06-16 22:26:36 -06:00
tangxifan 9d0e002532 echo path in architecture bitstream database 2020-06-16 21:29:45 -06:00
ganeshgore 559564c333 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-06-12 17:31:14 -06:00
tangxifan a5055e9d26 add support about loading external fabric key 2020-06-12 13:03:11 -06:00
tangxifan 9dbf536306 add shuffled configurable children support for top module 2020-06-12 11:16:53 -06:00
tangxifan cf9c3b0f44 add write fabric to test cases 2020-06-12 10:50:23 -06:00
tangxifan 3499b4d3e7 add fabric key writer for top-level module 2020-06-12 10:41:34 -06:00
tangxifan 278acee216 bug fix for 'build_fabric' command 2020-06-11 23:59:24 -06:00
tangxifan 9167b288b6 add options for fabric key 2020-06-11 21:50:46 -06:00
tangxifan 8a4ec85c39 add configurable children-related methods to module manager 2020-06-11 21:44:25 -06:00
tangxifan 58807bfcb3 remove simulation settings from openfpga arch data structure 2020-06-11 19:31:16 -06:00
tangxifan 96b58dfdbb use new simulation setting command in openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan 4a2f6dfae2 add read/write simulation setting commands to openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan 3c10af7f2b bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm 2020-06-11 19:31:14 -06:00
tangxifan 8267dad8ef add decoder support for Z signals 2020-06-11 19:31:14 -06:00
tangxifan 5368485bd6 keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level 2020-06-11 19:31:14 -06:00
tangxifan c85ccceac7 try bug fixing in memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 0bee70bee6 finish memory bank configuration protocol support. 2020-06-11 19:31:13 -06:00
tangxifan e14c39e14c update Verilog full testbench generation to support memory bank configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan 51e1559352 add fabric bitstream support for memory bank configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan 0e16ee1030 add configuration bus nets for memory bank decoders at top module 2020-06-11 19:31:13 -06:00
tangxifan fa8dfc1fbd add configuration protocol ports to top module for memory bank organization 2020-06-11 19:31:13 -06:00
tangxifan ad7422359d deploy compact constant values in Verilog codes 2020-06-11 19:31:13 -06:00
tangxifan 8ec8ac4118 bug fixed in flatten memory organization. Passed verification 2020-06-11 19:31:12 -06:00
tangxifan b9aac3cbdf updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan fbe05963e0 add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol) 2020-06-11 19:31:12 -06:00
tangxifan d2d443a988 start developing memory bank and standalone configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan 9e176b8d38 add fast configuration stats to log 2020-06-11 19:31:12 -06:00
tangxifan 8b3e79766c add fast configuration option to fpga_verilog to speed up full testbench simulation 2020-06-11 19:31:12 -06:00
tangxifan b5e5182f52 frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops 2020-06-11 19:31:11 -06:00
tangxifan 31c9a011dd keep bug fixing for arch decoders 2020-06-11 19:31:11 -06:00
tangxifan bdc9efb38f bug fix in top-level testbench for frame-based decoders 2020-06-11 19:31:11 -06:00
tangxifan 986956e474 bug fix for arch decoder Verilog codes. Now Modelsim compiles ok. 2020-06-11 19:31:11 -06:00
tangxifan 6a72c66eb8 bug fixed for frame-based configuration memory in top-level full testbench 2020-06-11 19:31:11 -06:00
tangxifan 8aa665b3b2 bug fix in the Verilog codes for frame decoders 2020-06-11 19:31:10 -06:00
tangxifan 8298bbff78 bug fixed in the fabric bitstream for frame-based configurable memories. 2020-06-11 19:31:10 -06:00
tangxifan bf9f62f0f7 keep bug fixing for frame-based configuration protocol. 2020-06-11 19:31:10 -06:00
tangxifan 65df309419 bug fixing for frame-based configuration protocol and rename some naming function to be generic 2020-06-11 19:31:10 -06:00
tangxifan ece651ade2 bug fixed in the configuration chian errrors 2020-06-11 19:31:10 -06:00
tangxifan cff5b5cfc1 break the configuration testbench. This commit is to spot which modification leads to the problem 2020-06-11 19:31:10 -06:00
tangxifan 85921dcc05 add fabric bitstream builder for frame-based configuration protocol 2020-06-11 19:31:10 -06:00
tangxifan 4a0e1cd908 add fabric bitstream data structure and deploy it to Verilog testbench generation 2020-06-11 19:31:10 -06:00
tangxifan 8c14cced84 start improve fabric bitstream database to support frame-based configuration protocol 2020-06-11 19:31:09 -06:00
tangxifan 5c5a044c68 add architecture decoder (for frame-based config memory) to Verilog writer 2020-06-11 19:31:09 -06:00
tangxifan c696e3d20f refine frame-based memory addition to compact the area 2020-06-11 19:31:09 -06:00
tangxifan ed2325ec9e add frame decoder build-up to top-level module 2020-06-11 19:31:09 -06:00
tangxifan 290dd1a8a6 add frame decoder builder to all the module graph builder except the top-level 2020-06-11 19:31:09 -06:00
tangxifan 8864920460 add frame-based memory module builder 2020-06-11 19:31:09 -06:00
tangxifan 3a26bb5eef add advanced check in configurable memories 2020-06-11 19:31:09 -06:00
tangxifan bba476fef4 add explicit port mapping support to Verilog testbench generator 2020-06-11 19:31:07 -06:00
tangxifan e089b0ef22 use constant string for inverted port naming 2020-06-11 19:31:07 -06:00
tangxifan 8915d10d27 add verbose output option to configure port disable timing writer 2020-06-11 19:31:07 -06:00
tangxifan 6177921d4c bug fixed in configure port disable timing. Now we disable the right ports of LUTs 2020-06-11 19:31:07 -06:00
tangxifan f52b5d5b4c use error code in read_arch command 2020-06-11 19:31:07 -06:00
tangxifan e9ceedb01b use constant openfpga context in SDC generator 2020-06-11 19:31:07 -06:00
tangxifan 067d09f954 bug fix for configure port disable_timing writer 2020-06-11 19:31:06 -06:00
tangxifan 13f591cacf add new command to disable timing for configure ports of programmable modules 2020-06-11 19:31:06 -06:00
tangxifan ae9f1fbd90 critical bug fixed in the disable MUX output 2020-06-11 19:31:06 -06:00
tangxifan 99751b84f5 bug fix in configuration chain sdc writer 2020-06-11 19:31:06 -06:00
tangxifan 02e86c565a bug fix in configuration chain SDC writer 2020-06-11 19:31:06 -06:00
tangxifan 4c0953415b add configuration chain sdc writer 2020-06-11 19:31:06 -06:00
tangxifan dad99d13a2 bug fixed in SDC timing writer for primitive pb_type 2020-06-11 19:31:06 -06:00
tangxifan 8d2360a710 simplify include_netlist.v 2020-06-11 19:31:05 -06:00
tangxifan b8a79c563d bug fix in the SDC port generation 2020-06-11 19:31:05 -06:00
tangxifan 84d24ad075 bug fix in pnr sdc grid writer for module paths in hierarchical view 2020-06-11 19:31:05 -06:00
tangxifan 99fa51cb49 bug fixed in the SDC CB hierarchy writer 2020-06-11 19:31:05 -06:00
tangxifan 10e1a4b2fe format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format 2020-06-11 19:31:05 -06:00
tangxifan cc6d988872 bug fix in grid SDC generator 2020-06-11 19:31:05 -06:00
tangxifan b167c85980 fully expand grid hierarchy in SDC writer 2020-06-11 19:31:05 -06:00
tangxifan 55518f4cec minor fix in the sdc hierarchy writer for grids 2020-06-11 19:31:05 -06:00
tangxifan b57a90a6ca add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints 2020-06-11 19:31:05 -06:00
tangxifan 5a8c05378e add --depth option to fabric hierarchy writer 2020-06-11 19:31:04 -06:00
tangxifan d9dc7160a7 minor fix on the hierarchy writer in SDC generator 2020-06-11 19:31:04 -06:00
tangxifan 17c254a370 add missing file to follow up the previous commit 2020-06-11 19:31:04 -06:00
tangxifan c651df6421 add hierarchy writer to SDC generator 2020-06-11 19:31:04 -06:00
tangxifan 6aff33dd35 add fabric hierarchy writer 2020-06-11 19:31:04 -06:00
tangxifan 0985c720e9 remove regexp in SDC generation. 2020-06-11 19:31:04 -06:00
tangxifan 8726c618eb add time unit support on SDC generator. Now users can define time_unit thru cmd-line options 2020-06-11 19:31:03 -06:00
tangxifan 0e44cf3ea3 now SDC to disable routing multiplexer outputs can use wildcards 2020-06-11 19:31:03 -06:00
tangxifan 609115e51f now hierarchical SDC generation is applicable to CB timing constraints 2020-06-11 19:31:03 -06:00
tangxifan 7e82c23f52 now add SDC generator supports both hierarchical and flatten in writing timing constraints 2020-06-11 19:31:03 -06:00
tangxifan 7503c58fb2 small fix on SDC generator for SB which do not exist in FPGA 2020-06-11 19:31:02 -06:00
tangxifan d0793d9029 now disable_sb_output support wildcard 2020-06-11 19:31:02 -06:00
tangxifan 8695c5ee78 add options to use general-purpose wildcards in SDC generator 2020-06-11 19:31:02 -06:00
tangxifan facd87dafe use wildcard in SDC generation for multiple-instanced-blocks 2020-06-11 19:31:02 -06:00
tangxifan 1e2226e1c3 now use explicit port mapping in the verilog testbenches for reference benchmarks 2020-06-11 19:31:02 -06:00
tangxifan 69306faf22 add a new include netlist for all the fabric-related netlists 2020-06-11 19:31:01 -06:00
tangxifan 8f5a684b10 removed redundant include files in all the verilog netlists except the top one 2020-06-11 19:28:13 -06:00
tangxifan 185e574738 removed redundant include files in all the verilog netlists except the top one 2020-04-24 20:21:32 -06:00
tangxifan e811f8bb21 plug in netlist manager and now the include_netlist appears in one unique file 2020-04-23 20:42:11 -06:00
tangxifan 87b17fc25f add netlist manager data structure 2020-04-23 18:59:09 -06:00
tangxifan bf841b9a8e bug fixed in identifying wired LUT 2020-04-22 17:28:16 -06:00
tangxifan 8ac6e10727 bug fix in lut and mux module generation on supporting spypads 2020-04-22 14:41:16 -06:00
tangxifan 73e9006372 add arch file with spy pads 2020-04-22 12:56:09 -06:00
tangxifan 9960625b01 add example spypad architecture 2020-04-22 11:10:59 -06:00
tangxifan 2e3054f79a bug fixed for SDC generation for LUTs 2020-04-21 14:34:51 -06:00
tangxifan 68b7991a46 bug fixed for sdc on memory blocks 2020-04-21 13:37:56 -06:00
tangxifan d325bede68 add fabric bitstream writer 2020-04-21 12:02:10 -06:00
tangxifan 3f1fb70d16 FPGA SDC now constrain max and min delay for primitive modules in grids 2020-04-21 11:00:28 -06:00
tangxifan c2804a4c1f bug fix for RC delay computing in SDC generation 2020-04-20 22:20:00 -06:00
tangxifan 1a8968cb37 now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML 2020-04-20 21:12:51 -06:00
tangxifan e10cafe0a5 Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
tangxifan 2e3a811f4f critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results 2020-04-18 21:04:46 -06:00
tangxifan a7d900088b now generating simulation ini file will try to create directory first 2020-04-15 20:53:37 -06:00
tangxifan 72e8824a87 bug fixed on removing undriven pins (direct connection between clbs) from cb 2020-04-15 20:41:15 -06:00
tangxifan 2ffd174e6a fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI 2020-04-15 15:48:33 -06:00
tangxifan 56e0d2a918 critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA 2020-04-13 12:58:44 -06:00
tangxifan 07a384e440 now use openfpga tokenizer to trim command line string in openfpga shell 2020-04-13 11:08:31 -06:00
tangxifan e6c896d583 now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
tangxifan b9dab2baaf add exit codes to command execution in shell context 2020-04-08 16:18:05 -06:00
tangxifan 1fb37f4c71 improve directory creator to support same functionality as 'mkdir -p' 2020-04-08 12:55:09 -06:00
tangxifan e31dc1f2f2 openfpga shell now support continued line charactor '\' 2020-04-07 21:27:51 -06:00
tangxifan 33315f0521 now openfpga shell allow empty space at beginning and end of each line in script mode 2020-04-07 20:46:45 -06:00
tangxifan 0b1c8ac139 bug fixed in identifying the physical interconnect for pb_graph nodes 2020-04-07 19:46:42 -06:00
tangxifan 62276f9e28 minor code format 2020-04-07 18:43:11 -06:00
tangxifan ff7ea99381 bug fixed in register scan-chain architecture 2020-04-07 17:06:16 -06:00
tangxifan 2342d7cdc6 minor tweak on the scan-chain support in VPR8 as well as architecture file
Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
2020-04-07 17:03:44 -06:00
tangxifan 50bb04d496 add scan-chain test case. Debugging on the way 2020-04-07 16:50:41 -06:00
tangxifan cbcd1d20d4 fixed memory leakage in pb_pin fixup 2020-04-07 16:24:04 -06:00
tangxifan 5a04da2082 fix memory leakage in openfpga title 2020-04-07 16:14:41 -06:00
tangxifan 6daee8c2c8 bug fixed in the example architecture 2020-04-07 16:03:34 -06:00
tangxifan 628ea3b654 improve adder chain arch XML to support sequential output for sumout 2020-04-07 15:39:37 -06:00
tangxifan 26d1261c1f add test cases using shift registers 2020-04-07 15:09:10 -06:00
tangxifan e61e7167b3 update circuit model names in the example tree-like MUX architecture 2020-04-07 11:27:16 -06:00
tangxifan 0eeb8e5317 clean up example architecture XML by removing redundant syntax 2020-04-07 11:24:42 -06:00
tangxifan 6d6295ef93 Add test cases about using standard cell mux2 2020-04-07 11:12:47 -06:00
tangxifan d39d7a68ce add test cases for using tree-like multiplexer 2020-04-07 10:46:49 -06:00
tangxifan 92a3a444f9 update VPR7 to support global I/O ports 2020-04-06 20:44:00 -06:00
tangxifan 13cd48c119 add support on packable/unpackable modes in VPR architecture 2020-04-06 16:07:49 -06:00
tangxifan 6eb125ec2a Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML 2020-04-06 14:09:52 -06:00
tangxifan 3369d724e9 bug fixing in Verilog top-level testbench generation 2020-04-05 17:50:11 -06:00
tangxifan decc1dc4b2 debugged global gp input/output port support 2020-04-05 17:39:30 -06:00
tangxifan bcb86801fa bug fixed in gpio naming for module manager ports 2020-04-05 17:26:44 -06:00
tangxifan 5f4e7dc5d4 support gpinput and gpoutput ports in module manager and circuit library 2020-04-05 16:52:21 -06:00
tangxifan bc47b3ca94 update verilog module writer to the global spy ports 2020-04-05 16:04:13 -06:00
tangxifan 8b583b7917 debugging spy port builder in module manager 2020-04-05 16:01:25 -06:00
tangxifan ca45efd13d add testing script for the spy io 2020-04-05 15:24:40 -06:00
tangxifan 3b63ad6657 add test openfpga arch XML with spy pad 2020-04-05 15:23:07 -06:00
tangxifan 836f722f20 start supporting global output ports in module manager 2020-04-05 15:19:46 -06:00
tangxifan 32c74ad811 added FPGA architecture with I/Os on the left and right sides 2020-04-01 15:46:38 -06:00
tangxifan 63306ce3a0 add comments to explain the memory organization in the top-level module 2020-04-01 11:05:30 -06:00
tangxifan 07e1979498 add architecture examples on wide memory blocks (width=2). tileable routing is working 2020-03-28 15:41:26 -06:00
tangxifan ff9cc50527 relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads 2020-03-27 20:09:50 -06:00
tangxifan e601a648cc relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics 2020-03-27 19:07:34 -06:00
tangxifan 34a1b61ecb add an example FPGA architecture with AIB interface at the right side of I/Os 2020-03-27 18:45:27 -06:00
tangxifan 4bf0a63ae6 bug fixed for multiple io types defined in FPGA architectures 2020-03-27 16:32:15 -06:00
tangxifan 7c9c2451f2 debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric 2020-03-27 16:03:42 -06:00
tangxifan b09b051249 add all the test cases considering tileable, carry chain, direct connection and memory blocks 2020-03-27 13:58:35 -06:00
tangxifan e47a0a4422 add through channel architecture example 2020-03-27 11:32:44 -06:00
tangxifan 91a618466d bug fixing for rr_graph.clear() function 2020-03-27 10:52:48 -06:00
tangxifan 329b0a9cf1 add options to enable SDC constraints on zero-delay paths 2020-03-25 15:55:30 -06:00
tangxifan 4a0128f240 minor fix on the SDC format 2020-03-25 14:46:31 -06:00
tangxifan c2e5d6b8e2 add options to dsiable SDC for non-clock global ports 2020-03-25 14:38:13 -06:00
tangxifan 787dc8ce83 added ASCII OpenFPGA logo in shell interface 2020-03-25 11:16:04 -06:00
tangxifan b6bdf78d95 bug fixed for heterogeneous block instances in top module 2020-03-24 17:39:26 -06:00
tangxifan 610c71671f experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
2020-03-24 16:47:45 -06:00
tangxifan 8a996ceae5 bug fixed in tileable routing when heterogeneous blocks are considered;
VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
tangxifan 08b46af7be add micro architecture for heterogeneous FPGA with single-mode DPRAM 2020-03-24 12:20:51 -06:00
tangxifan 9e4e12aae9 fixed echo message in the compression rate of gsb uniquifying 2020-03-22 16:13:04 -06:00
tangxifan ff474d87de fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs 2020-03-22 16:11:00 -06:00
tangxifan fdf6a6bd3e use chan_node_in_edges from rr_gsb in XML writer 2020-03-22 15:48:11 -06:00
tangxifan 3958ac2494 fix bugs in flow manager on default compress routing problems 2020-03-22 15:26:15 -06:00
tangxifan fc6abc13fd add physical tile utils to identify pins that have Fc=0 2020-03-21 21:02:47 -06:00
tangxifan 7b9384f3b2 add write_gsb command to shell interface 2020-03-21 19:40:26 -06:00
tangxifan 637be076dc adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working 2020-03-21 18:49:20 -06:00
tangxifan 9a518e8bb6 bug fixed for tileable rr_graph builder for more 4x4 fabrics 2020-03-21 18:07:00 -06:00
tangxifan 63c4669dbb fixed bug in the fast look-up for tileable rr_graph 2020-03-21 17:36:08 -06:00
tangxifan c0e8d98c6f bug fixed in tile direct builder 2020-03-21 12:43:56 -06:00
tangxifan 8f35f191eb use the formalized function in FPGA-SDC to identify direct connection 2020-03-21 11:42:00 -06:00
tangxifan 28123b8052 remove the direct connected IPIN/OPIN from RR GSB builder 2020-03-21 11:38:39 -06:00
tangxifan 2ff2d65e58 start debugging tileable routing using larger array size. Bug spotted in finding chan nodes 2020-03-20 22:12:23 -06:00
tangxifan 682b667a3c minor bug fix for direct connection in FPGA-SDC 2020-03-20 21:44:01 -06:00
tangxifan 05ec86430a temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT! 2020-03-20 17:56:03 -06:00
tangxifan 3c37b33f17 critical bug fixed in edge sorting for rr_gsb 2020-03-20 17:45:50 -06:00
tangxifan 2c0c5a061b spot a bug in assigning rr_switch in tileable routing 2020-03-20 16:53:43 -06:00
tangxifan 708fda9606 fixed a bug in using tileable routing when directlist is enabled 2020-03-20 16:38:58 -06:00
tangxifan c5049a1ec8 keep debugging tile direct connections 2020-03-20 15:10:00 -06:00
tangxifan a46fc9f028 add debugging information for tile direct builder 2020-03-20 14:59:46 -06:00
tangxifan 9837be618d start debugging tile direct with micro architecture 2020-03-20 14:52:52 -06:00
tangxifan a0b150f12e adding micro architecture using adder chain 2020-03-20 14:18:59 -06:00
tangxifan 8d57808d07 add missing files for micro benchmarks 2020-03-20 11:08:55 -06:00
tangxifan 808853db0b critical bug fixed for find proper pb_route traceback 2020-03-13 12:26:37 -06:00
tangxifan 81e5af464e improve lb_route to avoid routing combinational loops 2020-03-12 23:58:56 -06:00
tangxifan 773e6da308 Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree 2020-03-12 22:53:17 -06:00
tangxifan f90dc5c296 remove redundant XML codes 2020-03-12 20:44:07 -06:00
tangxifan 29450f3472 debugging multi-source lb router 2020-03-12 20:42:41 -06:00
tangxifan 8921905bec annotate multiple-source and multiple-sink nets from pb to lb router 2020-03-12 19:21:13 -06:00
tangxifan f0b22aaa11 Make lb router support multiple sources to be routed 2020-03-12 13:44:14 -06:00
tangxifan c40675ca9d minor code formatting 2020-03-12 11:55:25 -06:00
tangxifan f1e8e78410 minor code formatting 2020-03-12 11:47:42 -06:00
tangxifan 689c50dff1 label the routing status for each sink in lb_router 2020-03-12 11:36:31 -06:00
tangxifan a1f19e776e Add comments to lb router and extract a private function for routing a single net 2020-03-12 11:05:38 -06:00
tangxifan cd50155e29 rename variables in lb router 2020-03-12 10:24:38 -06:00
tangxifan 17a1c61b9d minor change in variable names in lb_router 2020-03-11 21:10:16 -06:00
tangxifan 8e796f152f add comments to lb_router about how-to-use 2020-03-11 21:05:06 -06:00
tangxifan 2a260a05aa add a microbenchmark `and_latch` to test LUTs in wired mode 2020-03-11 10:40:59 -06:00
tangxifan aff73bdd74 deployed edge sorting and make it as an option to link_arch command 2020-03-08 15:59:53 -06:00
tangxifan b80e26e711 update bitstream generator to use sorted edges 2020-03-08 15:36:47 -06:00
tangxifan 5558932762 use sorted edges in building routing modules 2020-03-08 15:31:41 -06:00
tangxifan f9499afe04 remove unused variable 2020-03-08 15:00:01 -06:00
tangxifan 0c7aa2581d update vpr8 version with hotfix on undriven pins in GSB 2020-03-08 14:58:56 -06:00
tangxifan ca92c2717f bug fix for tile directs 2020-03-07 16:00:32 -07:00
tangxifan 37423729ec bug fixing for naming the duplicated pins 2020-03-07 15:44:57 -07:00
tangxifan 5be118d695 tileable rr_graph builder ready to debug 2020-03-06 16:18:45 -07:00
tangxifan 6e83154703 move rr_gsb and rr_chan to tileable rr_graph builder 2020-03-04 14:14:28 -07:00
tangxifan 4b7d2221d1 adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr 2020-03-04 13:55:53 -07:00
tangxifan 7fcd27e000 now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer 2020-03-03 12:29:58 -07:00
tangxifan 3241d8bd37 put analysis sdc writer online. Minor bug in redudant '/' to be fixed 2020-03-02 19:54:18 -07:00
tangxifan 037c7e5c43 adapt top-level function for analysis SDC writer 2020-03-02 17:58:44 -07:00
tangxifan 24f7416c71 adapt analysis SDC writer for grids 2020-03-02 17:15:01 -07:00
tangxifan 6474183539 adapt analysis SDC writer for routing modules 2020-03-02 14:29:58 -07:00
tangxifan 543cff58b9 start porting analysis SDC writer 2020-03-02 13:44:08 -07:00
tangxifan a17c14c363 clean-up command addition and add fabric bitstream building to sample script 2020-03-02 10:39:19 -07:00
tangxifan aa66042dfb move simulation setting annotation to a separated source file 2020-02-29 15:19:02 -07:00
tangxifan 7b18f7cd09 now the auto select number of clocks in simulation is online 2020-02-29 13:29:16 -07:00
tangxifan 3807a940f4 fixed critical bugs in bitstream generation and now we pass microbenchmarks 2020-02-28 16:45:50 -07:00
tangxifan 9fd184e3ab rm out-of-date script 2020-02-28 15:42:18 -07:00
tangxifan 05ebd77d7d start debugging with micro benchmarks. Spot problem in local routing 2020-02-28 15:41:32 -07:00
tangxifan a6c2d2c7d1 bug fixed for io location mapping 2020-02-28 14:46:01 -07:00
tangxifan 80bb2baae5 start verification and bug fixing 2020-02-28 14:29:01 -07:00
tangxifan 542fadaaae allow users to use VPR critical path delay in OpenFPGA simulation 2020-02-28 12:10:27 -07:00
tangxifan de8425874c use user defined critical path delay in SDC generation 2020-02-28 11:24:39 -07:00
tangxifan 092e10afda bring pnr sdc generator online and fixed minor bugs in bitstream writing 2020-02-28 11:14:50 -07:00
tangxifan e45fa18c4c adapt PnR SDC writer 2020-02-28 10:06:35 -07:00
tangxifan 89c51b70e3 split sdc option into two categories which will be called by different commands 2020-02-28 09:48:58 -07:00
tangxifan fdcb982903 adapt pnr sdc grid writer 2020-02-27 21:06:33 -07:00
tangxifan b4ed931ac6 adapt sdc routing writer 2020-02-27 20:35:56 -07:00
tangxifan d136ac236f adapt sdc memory utils 2020-02-27 19:39:57 -07:00
tangxifan 78476ca774 adapt sdc writer utils 2020-02-27 19:36:28 -07:00
tangxifan 8322b1623d start porting SDC generator 2020-02-27 19:30:36 -07:00
tangxifan 65c81e14b2 add simulation ini file writer 2020-02-27 18:01:47 -07:00
tangxifan ae899f3b11 bug fixed for clock names 2020-02-27 16:51:55 -07:00
tangxifan 9b769cd8e4 bug fix for using renamed i/o names 2020-02-27 16:37:20 -07:00
tangxifan b010fc1983 add warning to force formal_verification_top_netlist enabled 2020-02-27 13:28:21 -07:00
tangxifan 078f72320f debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports 2020-02-27 13:24:26 -07:00
tangxifan f558405887 ported verilog testbench generator online. Split from fabric generator. Testing to be done 2020-02-27 12:33:09 -07:00
tangxifan 77529f4957 adapt top Verilog testbench generation 2020-02-26 21:30:21 -07:00
tangxifan bb671acac3 add formal random Verilog testbench generation 2020-02-26 20:58:16 -07:00
tangxifan e9adb4fdbc add preconfig top module Verilog generation 2020-02-26 20:38:01 -07:00
tangxifan b3796b0818 build io location map 2020-02-26 19:58:18 -07:00
tangxifan 25e0583636 add io location map data structure and start porting verilog testbench generator 2020-02-26 17:10:57 -07:00
tangxifan 410dcf6ab6 debugged LUT bitstream 2020-02-26 11:42:18 -07:00
tangxifan a26d31b87f make write bitstream online 2020-02-26 11:09:23 -07:00
tangxifan 759758421d found the bug in physical pb mode bits and fixed 2020-02-25 23:45:49 -07:00
tangxifan 075264e3e3 debugging LUT bitstream generation 2020-02-25 23:29:16 -07:00