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update bitstream generator to use sorted edges

This commit is contained in:
tangxifan 2020-03-08 15:36:47 -06:00
parent 5558932762
commit b80e26e711
6 changed files with 26 additions and 25 deletions
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19
openfpga/src/fabric/build_routing_module_utils.cpp
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@ -17,25 +17,6 @@
/* begin namespace openfpga */
namespace openfpga {
/************************************************************************
* Find the configurable driver nodes for a node in the rr_graph
***********************************************************************/
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const size_t& track_id) {
std::vector<RRNodeId> driver_nodes;
for (const RREdgeId& edge : rr_gsb.get_chan_node_in_edges(rr_graph, chan_side, track_id)) {
/* Bypass non-configurable edges */
if (false == rr_graph.edge_is_configurable(edge)) {
continue;
}
driver_nodes.push_back(rr_graph.edge_src_node(edge));
}
return driver_nodes;
}
/*********************************************************************
* Generate a port for a routing track of a swtich block
********************************************************************/

5
openfpga/src/fabric/build_routing_module_utils.h
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@ -17,11 +17,6 @@
/* begin namespace openfpga */
namespace openfpga {
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const size_t& track_id);
ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,

1
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -19,6 +19,7 @@
#include "openfpga_reserved_words.h"
#include "openfpga_naming.h"
#include "rr_gsb_utils.h"
#include "openfpga_rr_graph_utils.h"
#include "module_manager_utils.h"
#include "build_module_graph_utils.h"

2
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -114,7 +114,7 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager,
/* Determine if the interc lies inside a channel wire, that is interc between segments */
if (false == rr_gsb.is_sb_node_passing_wire(rr_graph, chan_side, chan_node_id)) {
driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
driver_rr_nodes = get_rr_gsb_chan_node_configurable_driver_nodes(rr_graph, rr_gsb, chan_side, chan_node_id);
/* Special: if there are zero-driver nodes. We skip here */
if (0 == driver_rr_nodes.size()) {
return;

19
openfpga/src/utils/rr_gsb_utils.cpp
View File

@ -36,4 +36,23 @@ bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
return routing_track_only;
}
/************************************************************************
* Find the configurable driver nodes for a node in the rr_graph
***********************************************************************/
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const size_t& track_id) {
std::vector<RRNodeId> driver_nodes;
for (const RREdgeId& edge : rr_gsb.get_chan_node_in_edges(rr_graph, chan_side, track_id)) {
/* Bypass non-configurable edges */
if (false == rr_graph.edge_is_configurable(edge)) {
continue;
}
driver_nodes.push_back(rr_graph.edge_src_node(edge));
}
return driver_nodes;
}
} /* end namespace openfpga */

5
openfpga/src/utils/rr_gsb_utils.h
View File

@ -18,6 +18,11 @@ namespace openfpga {
bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
const t_rr_type& cb_type);
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const size_t& track_id);
} /* end namespace openfpga */
#endif