update bitstream generator to use sorted edges
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parent
5558932762
commit
b80e26e711
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@ -17,25 +17,6 @@
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/* begin namespace openfpga */
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namespace openfpga {
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/************************************************************************
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* Find the configurable driver nodes for a node in the rr_graph
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***********************************************************************/
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std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const e_side& chan_side,
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const size_t& track_id) {
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std::vector<RRNodeId> driver_nodes;
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for (const RREdgeId& edge : rr_gsb.get_chan_node_in_edges(rr_graph, chan_side, track_id)) {
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/* Bypass non-configurable edges */
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if (false == rr_graph.edge_is_configurable(edge)) {
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continue;
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}
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driver_nodes.push_back(rr_graph.edge_src_node(edge));
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}
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return driver_nodes;
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}
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/*********************************************************************
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* Generate a port for a routing track of a swtich block
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********************************************************************/
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@ -17,11 +17,6 @@
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/* begin namespace openfpga */
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namespace openfpga {
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std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const e_side& chan_side,
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const size_t& track_id);
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ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager,
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const ModuleId& sb_module,
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const RRGraph& rr_graph,
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@ -19,6 +19,7 @@
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "rr_gsb_utils.h"
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#include "openfpga_rr_graph_utils.h"
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#include "module_manager_utils.h"
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#include "build_module_graph_utils.h"
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@ -114,7 +114,7 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager,
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/* Determine if the interc lies inside a channel wire, that is interc between segments */
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if (false == rr_gsb.is_sb_node_passing_wire(rr_graph, chan_side, chan_node_id)) {
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driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
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driver_rr_nodes = get_rr_gsb_chan_node_configurable_driver_nodes(rr_graph, rr_gsb, chan_side, chan_node_id);
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/* Special: if there are zero-driver nodes. We skip here */
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if (0 == driver_rr_nodes.size()) {
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return;
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@ -36,4 +36,23 @@ bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
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return routing_track_only;
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}
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/************************************************************************
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* Find the configurable driver nodes for a node in the rr_graph
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***********************************************************************/
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std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const e_side& chan_side,
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const size_t& track_id) {
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std::vector<RRNodeId> driver_nodes;
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for (const RREdgeId& edge : rr_gsb.get_chan_node_in_edges(rr_graph, chan_side, track_id)) {
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/* Bypass non-configurable edges */
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if (false == rr_graph.edge_is_configurable(edge)) {
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continue;
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}
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driver_nodes.push_back(rr_graph.edge_src_node(edge));
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}
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return driver_nodes;
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}
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} /* end namespace openfpga */
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@ -18,6 +18,11 @@ namespace openfpga {
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bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
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const t_rr_type& cb_type);
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std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const e_side& chan_side,
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const size_t& track_id);
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} /* end namespace openfpga */
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#endif
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