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bug fix for using renamed i/o names

This commit is contained in:
tangxifan 2020-02-27 16:37:20 -07:00
parent b010fc1983
commit 9b769cd8e4
11 changed files with 163 additions and 46 deletions
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1
openfpga/src/base/openfpga_verilog.cpp
View File

@ -82,6 +82,7 @@ void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
g_vpr_ctx.atom(),
g_vpr_ctx.placement(),
openfpga_ctx.io_location_map(),
openfpga_ctx.vpr_netlist_annotation(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().sim_setting,
openfpga_ctx.arch().config_protocol.type(),

4
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -139,6 +139,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const CircuitLibrary& circuit_lib,
const SimulationSetting& simulation_setting,
const e_config_protocol_type& config_protocol_type,
@ -169,6 +170,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
print_verilog_preconfig_top_module(module_manager, bitstream_manager,
circuit_lib, global_ports,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
netlist_name,
formal_verification_top_netlist_file_path,
src_dir_path);
@ -182,6 +184,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
random_top_testbench_file_path,
src_dir_path,
atom_ctx,
netlist_annotation,
simulation_setting);
}
@ -194,6 +197,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
config_protocol_type,
circuit_lib, global_ports,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
netlist_name,
top_testbench_file_path,
src_dir_path,

2
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -16,6 +16,7 @@
#include "bitstream_manager.h"
#include "simulation_setting.h"
#include "io_location_map.h"
#include "vpr_netlist_annotation.h"
#include "fabric_verilog_options.h"
#include "verilog_testbench_options.h"
@ -40,6 +41,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const CircuitLibrary& circuit_lib,
const SimulationSetting& simulation_parameters,
const e_config_protocol_type& config_protocol_type,

32
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -55,7 +55,8 @@ static
void print_verilog_top_random_testbench_ports(std::fstream& fp,
const std::string& circuit_name,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx) {
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
/* Validate the file stream */
valid_file_stream(fp);
@ -72,7 +73,7 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
print_verilog_testbench_shared_ports(fp, atom_ctx,
print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
@ -94,7 +95,8 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
static
void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx) {
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
/* Validate the file stream */
valid_file_stream(fp);
@ -111,7 +113,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
std::string(),
std::string(),
std::string(BENCHMARK_PORT_POSTFIX),
atom_ctx,
atom_ctx, netlist_annotation,
false);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -132,7 +134,8 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
static
void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
const std::string& circuit_name,
const AtomContext& atom_ctx) {
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
/* Validate the file stream */
valid_file_stream(fp);
@ -144,7 +147,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
atom_ctx,
atom_ctx, netlist_annotation,
true);
print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
@ -182,6 +185,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const SimulationSetting& simulation_parameters) {
std::string timer_message = std::string("Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by '") + circuit_name.c_str() + std::string("'");
@ -208,13 +212,13 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
/* Start of testbench */
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx);
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation);
/* Call defined top-level module */
print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx);
print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx, netlist_annotation);
/* Call defined benchmark */
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx);
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx, netlist_annotation);
/* Find clock port to be used */
BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
@ -222,8 +226,10 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
/* Add stimuli for reset, set, clock and iopad signals */
print_verilog_testbench_clock_stimuli(fp, simulation_parameters,
clock_port);
print_verilog_testbench_random_stimuli(fp, atom_ctx,
std::string(CHECKFLAG_PORT_POSTFIX), clock_port);
print_verilog_testbench_random_stimuli(fp, atom_ctx,
netlist_annotation,
std::string(CHECKFLAG_PORT_POSTFIX),
clock_port);
print_verilog_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
@ -233,7 +239,9 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(ERROR_COUNTER),
atom_ctx,
clock_port_names, std::string(DEFAULT_CLOCK_NAME));
netlist_annotation,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
simulation_parameters.num_clock_cycles(),

1
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
View File

@ -19,6 +19,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const SimulationSetting& simulation_parameters);
} /* end namespace openfpga */

18
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -34,7 +34,8 @@ namespace openfpga {
static
void print_verilog_preconfig_top_module_ports(std::fstream& fp,
const std::string& circuit_name,
const AtomContext& atom_ctx) {
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
/* Validate the file stream */
valid_file_stream(fp);
@ -58,11 +59,18 @@ void print_verilog_preconfig_top_module_ports(std::fstream& fp,
&& (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
if (0 < port_counter) {
fp << "," << std::endl;
}
/* Both input and output ports have only size of 1 */
BasicPort module_port(std::string(atom_ctx.nlist.block_name(atom_blk) + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)), 1);
BasicPort module_port(std::string(block_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)), 1);
fp << generate_verilog_port(port_type2type_map[atom_ctx.nlist.block_type(atom_blk)], module_port);
/* Update port counter */
@ -375,6 +383,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir) {
@ -400,7 +409,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));
/* Print module declaration and ports */
print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx);
print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx, netlist_annotation);
/* Find the top_module */
ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
@ -423,7 +432,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
/* Connect I/Os to benchmark I/Os or constant driver */
print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
atom_ctx, place_ctx, io_location_map,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);

2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
View File

@ -11,6 +11,7 @@
#include "module_manager.h"
#include "bitstream_manager.h"
#include "io_location_map.h"
#include "vpr_netlist_annotation.h"
/********************************************************************
* Function declaration
@ -26,6 +27,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir);

118
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -58,6 +58,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& module_output_port_postfix,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const bool& use_explicit_port_map) {
/* Validate the file stream */
valid_file_stream(fp);
@ -71,6 +72,13 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
&& (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* The first port does not need a comma */
if(0 < port_counter){
fp << "," << std::endl;
@ -79,9 +87,9 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t";
if (true == use_explicit_port_map) {
fp << "." << atom_ctx.nlist.block_name(atom_blk) << module_input_port_postfix << "(";
fp << "." << block_name << module_input_port_postfix << "(";
}
fp << atom_ctx.nlist.block_name(atom_blk);
fp << block_name;
if (true == use_explicit_port_map) {
fp << ")";
}
@ -89,9 +97,9 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
VTR_ASSERT_SAFE(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
fp << "\t\t";
if (true == use_explicit_port_map) {
fp << "." << atom_ctx.nlist.block_name(atom_blk) << module_output_port_postfix << "(";
fp << "." << block_name << module_output_port_postfix << "(";
}
fp << atom_ctx.nlist.block_name(atom_blk) << output_port_postfix;
fp << block_name << output_port_postfix;
if (true == use_explicit_port_map) {
fp << ")";
}
@ -115,6 +123,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const size_t& unused_io_value) {
@ -152,21 +161,27 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
VTR_ASSERT(io_index < module_mapped_io_port.get_width());
module_mapped_io_port.set_width(io_index, io_index);
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1
* In addition, the input and output ports may have different postfix in naming
* due to verification context! Here, we give full customization on naming
*/
BasicPort benchmark_io_port;
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
benchmark_io_port.set_name(std::string(atom_ctx.nlist.block_name(atom_blk) + io_input_port_name_postfix));
benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix));
benchmark_io_port.set_width(1);
print_verilog_comment(fp, std::string("----- Blif Benchmark input " + atom_ctx.nlist.block_name(atom_blk) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
print_verilog_comment(fp, std::string("----- Blif Benchmark input " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
} else {
VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
benchmark_io_port.set_name(std::string(atom_ctx.nlist.block_name(atom_blk) + io_output_port_name_postfix));
benchmark_io_port.set_name(std::string(block_name + io_output_port_name_postfix));
benchmark_io_port.set_width(1);
print_verilog_comment(fp, std::string("----- Blif Benchmark output " + atom_ctx.nlist.block_name(atom_blk) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
print_verilog_comment(fp, std::string("----- Blif Benchmark output " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false);
}
@ -281,6 +296,7 @@ void print_verilog_testbench_check(std::fstream& fp,
const std::string& check_flag_port_postfix,
const std::string& error_counter_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& default_clock_name) {
@ -314,14 +330,20 @@ void print_verilog_testbench_check(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t\tif(!(" << atom_ctx.nlist.block_name(atom_blk) << fpga_port_postfix;
fp << " === " << atom_ctx.nlist.block_name(atom_blk) << benchmark_port_postfix;
fp << ") && !(" << atom_ctx.nlist.block_name(atom_blk) << benchmark_port_postfix;
fp << "\t\t\tif(!(" << block_name << fpga_port_postfix;
fp << " === " << block_name << benchmark_port_postfix;
fp << ") && !(" << block_name << benchmark_port_postfix;
fp << " === 1'bx)) begin" << std::endl;
fp << "\t\t\t\t" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << " <= 1'b1;" << std::endl;
fp << "\t\t\t\t" << block_name << check_flag_port_postfix << " <= 1'b1;" << std::endl;
fp << "\t\t\tend else begin" << std::endl;
fp << "\t\t\t\t" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << "<= 1'b0;" << std::endl;
fp << "\t\t\t\t" << block_name << check_flag_port_postfix << "<= 1'b0;" << std::endl;
fp << "\t\t\tend" << std::endl;
}
}
@ -337,10 +359,16 @@ void print_verilog_testbench_check(std::fstream& fp,
continue;
}
fp << "\talways@(posedge " << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << ") begin" << std::endl;
fp << "\t\tif(" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << ") begin" << std::endl;
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
fp << "\talways@(posedge " << block_name << check_flag_port_postfix << ") begin" << std::endl;
fp << "\t\tif(" << block_name << check_flag_port_postfix << ") begin" << std::endl;
fp << "\t\t\t" << error_counter_name << " = " << error_counter_name << " + 1;" << std::endl;
fp << "\t\t\t$display(\"Mismatch on " << atom_ctx.nlist.block_name(atom_blk) << fpga_port_postfix << " at time = " << std::string("%t") << "\", $realtime);" << std::endl;
fp << "\t\t\t$display(\"Mismatch on " << block_name << fpga_port_postfix << " at time = " << std::string("%t") << "\", $realtime);" << std::endl;
fp << "\t\tend" << std::endl;
fp << "\tend" << std::endl;
@ -393,6 +421,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
*******************************************************************/
void print_verilog_testbench_random_stimuli(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::string& check_flag_port_postfix,
const BasicPort& clock_port) {
/* Validate the file stream */
@ -409,9 +438,15 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << atom_ctx.nlist.block_name(atom_blk) << " <= 1'b0;" << std::endl;
fp << "\t\t" << block_name << " <= 1'b0;" << std::endl;
}
}
@ -425,8 +460,14 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + check_flag_port_postfix), 1);
BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1);
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
}
@ -463,9 +504,15 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << atom_ctx.nlist.block_name(atom_blk) << " <= $random;" << std::endl;
fp << "\t\t" << block_name << " <= $random;" << std::endl;
}
}
@ -486,6 +533,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
*******************************************************************/
void print_verilog_testbench_shared_ports(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
@ -501,10 +549,16 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* TODO: Skip clocks because they are handled in another function */
/* Each logical block assumes a single-width port */
BasicPort input_port(atom_ctx.nlist.block_name(atom_blk), 1);
BasicPort input_port(block_name, 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl;
}
@ -520,8 +574,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + fpga_output_port_postfix), 1);
BasicPort output_port(std::string(block_name + fpga_output_port_postfix), 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl;
}
@ -542,8 +602,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + benchmark_output_port_postfix), 1);
BasicPort output_port(std::string(block_name + benchmark_output_port_postfix), 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl;
}
@ -558,8 +624,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + check_flag_port_postfix), 1);
BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, output_port) << ";" << std::endl;
}

6
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -10,6 +10,7 @@
#include "module_manager.h"
#include "vpr_context.h"
#include "io_location_map.h"
#include "vpr_netlist_annotation.h"
#include "simulation_setting.h"
/********************************************************************
@ -31,6 +32,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& module_output_port_postfix,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const bool& use_explicit_port_map);
void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
@ -39,6 +41,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const size_t& unused_io_value);
@ -62,6 +65,7 @@ void print_verilog_testbench_check(std::fstream& fp,
const std::string& check_flag_port_postfix,
const std::string& error_counter_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& default_clock_name);
@ -71,11 +75,13 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
void print_verilog_testbench_random_stimuli(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::string& check_flag_port_postfix,
const BasicPort& clock_port);
void print_verilog_testbench_shared_ports(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,

23
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -307,6 +307,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const e_config_protocol_type& sram_orgz_type,
const std::string& circuit_name){
@ -397,7 +398,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
print_verilog_wire_connection(fp, clock_port, op_clock_port, false);
}
print_verilog_testbench_shared_ports(fp, atom_ctx,
print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
@ -416,7 +417,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
static
void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx) {
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
/* Validate the file stream */
valid_file_stream(fp);
@ -433,7 +435,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
std::string(),
std::string(),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
atom_ctx,
atom_ctx, netlist_annotation,
false);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -766,6 +768,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
@ -799,7 +802,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Start of testbench */
print_verilog_top_testbench_ports(fp, module_manager, top_module,
atom_ctx, clock_port_names,
atom_ctx, netlist_annotation, clock_port_names,
sram_orgz_type, circuit_name);
/* Find the clock period */
@ -829,7 +832,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Connect I/Os to benchmark I/Os or constant driver */
print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
atom_ctx, place_ctx, io_location_map,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
std::string(),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
@ -837,7 +841,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Instanciate input benchmark */
print_verilog_top_testbench_benchmark_instance(fp,
circuit_name,
atom_ctx);
atom_ctx,
netlist_annotation);
/* Print tasks used for loading bitstreams */
print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type);
@ -848,6 +853,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Add stimuli for reset, set, clock and iopad signals */
print_verilog_testbench_random_stimuli(fp, atom_ctx,
netlist_annotation,
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1));
@ -859,7 +865,10 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
atom_ctx, clock_port_names, std::string(TOP_TB_OP_CLOCK_PORT_NAME));
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(TOP_TB_OP_CLOCK_PORT_NAME));
/* Find simulation time */
float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE,

2
openfpga/src/fpga_verilog/verilog_top_testbench.h
View File

@ -11,6 +11,7 @@
#include "circuit_library.h"
#include "vpr_context.h"
#include "io_location_map.h"
#include "vpr_netlist_annotation.h"
#include "simulation_setting.h"
/********************************************************************
@ -29,6 +30,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,