critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
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@ -289,6 +289,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
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/* Record memory-related information */
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module_manager.add_configurable_child(primitive_module, memory_module, memory_instance_id);
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}
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/* Add all the nets to connect configuration ports from memory module to primitive modules
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* This is a one-shot addition that covers all the memory modules in this primitive module!
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*/
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@ -292,7 +292,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
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/* Add all the nets to connect configuration ports from memory module to primitive modules
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* This is a one-shot addition that covers all the memory modules in this primitive module!
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*/
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if (false == memory_modules.empty()) {
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if (0 < module_manager.configurable_children(primitive_module).size()) {
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add_module_nets_memory_config_bus(module_manager, primitive_module,
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sram_orgz_type, circuit_lib.design_tech_type(sram_model));
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}
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