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critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA

This commit is contained in:
tangxifan 2020-04-13 12:58:44 -06:00
parent 07a384e440
commit 56e0d2a918
2 changed files with 2 additions and 1 deletions
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1
openfpga/src/fabric/build_grid_modules.cpp
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@ -289,6 +289,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
/* Record memory-related information */
module_manager.add_configurable_child(primitive_module, memory_module, memory_instance_id);
}
/* Add all the nets to connect configuration ports from memory module to primitive modules
* This is a one-shot addition that covers all the memory modules in this primitive module!
*/

2
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
View File

@ -292,7 +292,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
/* Add all the nets to connect configuration ports from memory module to primitive modules
* This is a one-shot addition that covers all the memory modules in this primitive module!
*/
if (false == memory_modules.empty()) {
if (0 < module_manager.configurable_children(primitive_module).size()) {
add_module_nets_memory_config_bus(module_manager, primitive_module,
sram_orgz_type, circuit_lib.design_tech_type(sram_model));
}