add physical tile utils to identify pins that have Fc=0

openfpga/src/fabric/build_grid_module_duplicated_pins.cpp

@@ -8,6 +8,8 @@
  *
  * Please follow this rules when creating new features!
  *******************************************************************/
+#include <algorithm>
+
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 
@@ -17,6 +19,8 @@
 #include "openfpga_naming.h"
 #include "openfpga_interconnect_types.h"
 
+#include "openfpga_physical_tile_utils.h"
+
 #include "build_grid_module_utils.h"
 #include "build_grid_module_duplicated_pins.h"
 
@@ -88,7 +92,8 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
            * we do not duplicate in these cases */
           if ( (RECEIVER == pin_class_type)
             /* Xifan: I assume that each direct connection pin must have Fc=0. */
-            || ( (DRIVER == pin_class_type) && (0. == grid_type_descriptor->fc_specs[ipin].fc_value) ) ) {
+            || ( (DRIVER == pin_class_type)
+              && (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)) ) ) {
             vtr::Point<size_t> dummy_coordinate;
             std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false);
             BasicPort grid_port(port_name, 0, 0);
@@ -169,7 +174,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
      * Follow the traditional recipe when adding nets!  
      * Xifan: I assume that each direct connection pin must have Fc=0. 
      */
-    if (0. == grid_type_descriptor->fc_specs[grid_pin_index].fc_value) {
+    if (0. == find_physical_tile_pin_Fc(grid_type_descriptor, grid_pin_index)) {
       /* Create a net to connect the grid pin to child module pin */
       ModuleNetId net = module_manager.create_module_net(grid_module);
       /* Find the port in grid_module */

openfpga/src/fabric/build_top_module_connection.cpp

@@ -12,6 +12,7 @@
 #include "openfpga_naming.h"
 #include "pb_type_utils.h"
 #include "rr_gsb_utils.h"
+#include "openfpga_physical_tile_utils.h"
 
 #include "build_top_module_utils.h"
 #include "build_top_module_connection.h"
@@ -232,7 +233,7 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
        * For other duplicated pins, we follow the new naming
        */
       std::string src_grid_port_name;
-      if (0. == grids[grid_coordinate.x()][grid_coordinate.y()].type->fc_specs[src_grid_pin_index].fc_value) {
+      if (0. == find_physical_tile_pin_Fc(grids[grid_coordinate.x()][grid_coordinate.y()].type, src_grid_pin_index)) {
         src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, 
                                                      rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
                                                      src_grid_pin_index, false);

openfpga/src/fabric/build_top_module_directs.cpp

@@ -96,8 +96,8 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
   std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false);
   ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); 
   if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) {
-    VTR_LOG_ERROR("Fail to find port '%s.%s'\n",
-                  src_module_name.c_str(),
+    VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n",
+                  src_module_name.c_str(), src_clb_coord.x(), src_clb_coord.y(),
                   src_port_name.c_str());
   }
   VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id));

openfpga/src/utils/openfpga_physical_tile_utils.cpp

@@ -0,0 +1,33 @@
+/***************************************************************************************
+ * This file includes most utilized functions that are used to acquire data from 
+ * VPR t_physical_tile_type 
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "openfpga_physical_tile_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Find the Fc of a pin in physical tile 
+ *******************************************************************/
+float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type,
+                                const int& pin) {
+  for (const t_fc_specification& fc_spec : type->fc_specs) {
+    if (fc_spec.pins.end() != std::find(fc_spec.pins.begin(), fc_spec.pins.end(), pin)) {
+      return fc_spec.fc_value; 
+    }
+  }
+  /* Every pin should have a Fc, give a wrong value */
+  VTR_LOGF_ERROR(__FILE__, __LINE__,
+                "Fail to find the Fc for %s.pin[%lu]\n",
+                type->name, pin);
+  exit(1);
+} 
+
+} /* end namespace openfpga */

openfpga/src/utils/openfpga_physical_tile_utils.h

@@ -0,0 +1,24 @@
+#ifndef OPENFPGA_PHYSICAL_TILE_UTILS_H
+#define OPENFPGA_PHYSICAL_TILE_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include <string>
+#include "physical_types.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type,
+                                const int& pin);
+
+
+} /* end namespace openfpga */
+
+#endif

openfpga/test_vpr_arch/k6_frac_N10_40nm.xml

@@ -77,13 +77,15 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <auto_layout aspect_ratio="1.0">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
-    </auto_layout>
+    </fixed_layout>
+    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 

openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml

@@ -161,7 +161,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>