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update verilog module writer to the global spy ports

This commit is contained in:
tangxifan 2020-04-05 16:04:13 -06:00
parent 8b583b7917
commit bc47b3ca94
1 changed files with 1 additions and 0 deletions
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openfpga/src/fpga_verilog/verilog_module_writer.cpp
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@ -396,6 +396,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
/* port type2type mapping */
std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT;
port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;