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debugged LUT bitstream

This commit is contained in:
tangxifan 2020-02-26 11:42:18 -07:00
parent a26d31b87f
commit 410dcf6ab6
3 changed files with 3 additions and 7 deletions
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3
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -406,9 +406,6 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager,
/* Generate bitstream for mode-select ports */
if (0 != lut_mode_select_ports.size()) {
std::vector<bool> mode_select_bitstream;
/* TODO: Xifan Tang: find out why some lut_pb has no mode bits!!!
* I suspect that wire LUTs are not mapped to any pb
*/
if (true == physical_pb.valid_pb_id(lut_pb_id)) {
mode_select_bitstream = generate_mode_select_bitstream(physical_pb.mode_bits(lut_pb_id));
} else { /* get default mode_bits */

5
openfpga/src/repack/build_physical_truth_table.cpp
View File

@ -98,10 +98,9 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb,
input_nets.push_back(physical_pb.pb_graph_pin_atom_net(lut_pb_id, &(pb_graph_node->input_pins[0][ipin])));
}
/* Find all the nets mapped to each outputs */
for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
const t_pb_graph_pin* output_pin = &(pb_graph_node->output_pins[iport][ipin]);
AtomNetId output_net = physical_pb.pb_graph_pin_atom_net(lut_pb_id, output_pin);
/* Bypass unmapped pins */

2
openfpga/src/repack/repack.cpp
View File

@ -292,7 +292,7 @@ void repack_cluster(const AtomContext& atom_ctx,
clustering_ctx.clb_nlist.block_pb(block_id)->pb_route,
atom_ctx,
device_annotation);
/* TODO: save routing results */
/* Save routing results */
save_lb_router_results_to_physical_pb(phy_pb, lb_router, lb_rr_graph);
VTR_LOGV(verbose, "Saved results in physical pb\n");