riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

make write bitstream online

This commit is contained in:
tangxifan 2020-02-26 11:09:23 -07:00
parent 759758421d
commit a26d31b87f
8 changed files with 69 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
openfpga/src/base/openfpga_bitstream.cpp
View File

@ -6,6 +6,8 @@
#include "vtr_log.h"
#include "build_device_bitstream.h"
#include "bitstream_writer.h"
#include "build_fabric_bitstream.h"
#include "openfpga_bitstream.h"
/* Include global variables of VPR */
@ -15,14 +17,35 @@
namespace openfpga {
/********************************************************************
* A wrapper function to call the fabric_verilog function of FPGA-Verilog
* A wrapper function to call the build_device_bitstream() in FPGA bitstream
*******************************************************************/
void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");
CommandOptionId opt_file = cmd.option("file");
openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx, openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx,
openfpga_ctx,
cmd_context.option_enable(cmd, opt_verbose));
if (true == cmd_context.option_enable(cmd, opt_file)) {
write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(),
cmd_context.option_value(cmd, opt_file));
}
}
/********************************************************************
* A wrapper function to call the build_fabric_bitstream() in FPGA bitstream
*******************************************************************/
void build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");
openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
openfpga_ctx.module_graph(),
cmd_context.option_enable(cmd, opt_verbose));
}
} /* end namespace openfpga */

3
openfpga/src/base/openfpga_bitstream.h
View File

@ -18,6 +18,9 @@ namespace openfpga {
void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context);
void build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context);
} /* end namespace openfpga */
#endif

22
openfpga/src/base/openfpga_bitstream_command.cpp
View File

@ -39,8 +39,12 @@ void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
* Command 'fpga_bitstream'
*/
Command shell_cmd_fpga_bitstream("fpga_bitstream");
/* Add an option '--file' in short '-f'*/
CommandOptionId fpga_bitstream_opt_file = shell_cmd_fpga_bitstream.add_option("file", true, "file path to output the bitstream database");
shell_cmd_fpga_bitstream.set_option_short_name(fpga_bitstream_opt_file, "f");
shell_cmd_fpga_bitstream.set_option_require_value(fpga_bitstream_opt_file, openfpga::OPT_STRING);
/* Add an option '--verbose' */
shell_cmd_fpga_bitstream.add_option("fabric_dependent", false, "Enable the bitstream construction for the FPGA fabric");
shell_cmd_fpga_bitstream.add_option("verbose", false, "Enable verbose output");
/* Add command 'fpga_bitstream' to the Shell */
@ -53,6 +57,22 @@ void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
cmd_dependency_fpga_bitstream.push_back(shell_cmd_repack_id);
shell.set_command_dependency(shell_cmd_fpga_bitstream_id, cmd_dependency_fpga_bitstream);
/********************************
* Command 'build_fabric_bitstream'
*/
Command shell_cmd_fabric_bitstream("build_fabric_bitstream");
/* Add an option '--verbose' */
shell_cmd_fabric_bitstream.add_option("verbose", false, "Enable verbose output");
/* Add command 'fabric_bitstream' to the Shell */
ShellCommandId shell_cmd_fabric_bitstream_id = shell.add_command(shell_cmd_fabric_bitstream, "Reorganize the fabric-independent bitstream for the FPGA fabric created by FPGA-Verilog");
shell.set_command_class(shell_cmd_fabric_bitstream_id, openfpga_bitstream_cmd_class);
shell.set_command_execute_function(shell_cmd_fabric_bitstream_id, build_fabric_bitstream);
/* The 'fabric_bitstream' command should NOT be executed before 'fpga_bitstream' */
std::vector<ShellCommandId> cmd_dependency_fabric_bitstream;
cmd_dependency_fabric_bitstream.push_back(shell_cmd_fpga_bitstream_id);
shell.set_command_dependency(shell_cmd_fabric_bitstream_id, cmd_dependency_fabric_bitstream);
}
} /* end namespace openfpga */

4
openfpga/src/base/openfpga_context.h
View File

@ -1,6 +1,7 @@
#ifndef OPENFPGA_CONTEXT_H
#define OPENFPGA_CONTEXT_H
#include <vector>
#include "vpr_context.h"
#include "openfpga_arch.h"
#include "vpr_netlist_annotation.h"
@ -56,6 +57,7 @@ class OpenfpgaContext : public Context {
const openfpga::ModuleManager& module_graph() const { return module_graph_; }
const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
public: /* Public mutators */
openfpga::Arch& mutable_arch() { return arch_; }
openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@ -69,6 +71,7 @@ class OpenfpgaContext : public Context {
openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
private: /* Internal data */
/* Data structure to store information from read_openfpga_arch library */
openfpga::Arch arch_;
@ -102,6 +105,7 @@ class OpenfpgaContext : public Context {
/* Bitstream database */
openfpga::BitstreamManager bitstream_manager_;
std::vector<openfpga::ConfigBitId> fabric_bitstream_;
/* Flow status */
openfpga::FlowManager flow_manager_;

7
openfpga/src/fpga_bitstream/bitstream_writer.cpp
View File

@ -111,7 +111,12 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
*******************************************************************/
void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager,
const std::string& fname) {
std::string timer_message = std::string("Writing ") + std::to_string(bitstream_manager.bits().size()) + std::string(" architecture independent bitstream into XML file '") + fname + std::string("'\n");
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
}
std::string timer_message = std::string("Write ") + std::to_string(bitstream_manager.bits().size()) + std::string(" architecture independent bitstream into XML file '") + fname + std::string("'");
vtr::ScopedStartFinishTimer timer(timer_message);
/* Create the file stream */

7
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
View File

@ -83,7 +83,8 @@ void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstre
* It was done in the function build_device_bitstream()
*******************************************************************/
std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
const ModuleManager& module_manager) {
const ModuleManager& module_manager,
const bool& verbose) {
std::vector<ConfigBitId> fabric_bitstream;
vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
@ -125,6 +126,10 @@ std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager
/* Ensure our fabric bitstream is in the same size as device bistream */
VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size());
VTR_LOGV(verbose,
"Built %lu configuration bits for fabric\n",
fabric_bitstream.size());
return fabric_bitstream;
}

3
openfpga/src/fpga_bitstream/build_fabric_bitstream.h
View File

@ -16,7 +16,8 @@
namespace openfpga {
std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
const ModuleManager& module_manager);
const ModuleManager& module_manager,
const bool& verbose);
} /* end namespace openfpga */

3
openfpga/test_script/s298_k6_frac.openfpga
View File

@ -30,7 +30,8 @@ build_fabric --compress_routing --duplicate_grid_pin #--verbose
repack --verbose
# Build the bitstream
fpga_bitstream --verbose
# - Output the fabric-independent bitstream to a file
fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
# Write the Verilog netlit for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist