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add fast configuration stats to log

This commit is contained in:
tangxifan 2020-05-29 18:22:36 -06:00
parent a5138113e4
commit 9e176b8d38
1 changed files with 8 additions and 0 deletions
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8
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -505,12 +505,17 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
case CONFIG_MEM_FRAME_BASED: {
/* For fast configuration, we will skip all the zero data points */
if (true == fast_configuration) {
size_t full_num_config_clock_cycles = num_config_clock_cycles;
num_config_clock_cycles = 1;
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
if (true == fabric_bitstream.bit_din(bit_id)) {
num_config_clock_cycles++;
}
}
VTR_LOG("Fast configuration reduces number of configuration clock cycles from %lu to %lu (compression_rate = %f%)\n",
full_num_config_clock_cycles,
num_config_clock_cycles,
100. * ((float)num_config_clock_cycles / (float)full_num_config_clock_cycles - 1.));
}
break;
}
@ -520,6 +525,9 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
exit(1);
}
VTR_LOG("Will use %ld configuration clock cycles to top testbench\n",
num_config_clock_cycles);
return num_config_clock_cycles;
}