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OpenFPGA
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bug fixed in tileable routing when heterogeneous blocks are considered; 

VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
This commit is contained in:
tangxifan 2020-03-24 13:02:35 -06:00
parent 08b46af7be
commit 8a996ceae5
2 changed files with 5 additions and 5 deletions
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2
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
View File

@ -193,7 +193,7 @@
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="false">
<layout tileable="tileable">
<!--auto_layout aspect_ratio="1.0"-->
<fixed_layout name="4x4" width="5" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->

8
vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
View File

@ -492,8 +492,8 @@ void load_one_grid_source_nodes_basic_info(RRGraph& rr_graph,
/* node bounding box */
rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
grid_coordinate.y(),
grid_coordinate.x(),
grid_coordinate.y()));
grid_coordinate.x() + cur_grid.type->width - 1,
grid_coordinate.y() + cur_grid.type->height - 1));
rr_graph.set_node_class_num(node, iclass);
rr_graph.set_node_capacity(node, 1);
@ -543,8 +543,8 @@ void load_one_grid_sink_nodes_basic_info(RRGraph& rr_graph,
/* node bounding box */
rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
grid_coordinate.y(),
grid_coordinate.x(),
grid_coordinate.y()));
grid_coordinate.x() + cur_grid.type->width - 1,
grid_coordinate.y() + cur_grid.type->height - 1));
rr_graph.set_node_class_num(node, iclass);
rr_graph.set_node_capacity(node, 1);