diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml index 850eb5450..87e6ff937 100644 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml +++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml @@ -193,7 +193,7 @@ - + diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 7191bc523..da77d536e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -492,8 +492,8 @@ void load_one_grid_source_nodes_basic_info(RRGraph& rr_graph, /* node bounding box */ rr_graph.set_node_bounding_box(node, vtr::Rect(grid_coordinate.x(), grid_coordinate.y(), - grid_coordinate.x(), - grid_coordinate.y())); + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1)); rr_graph.set_node_class_num(node, iclass); rr_graph.set_node_capacity(node, 1); @@ -543,8 +543,8 @@ void load_one_grid_sink_nodes_basic_info(RRGraph& rr_graph, /* node bounding box */ rr_graph.set_node_bounding_box(node, vtr::Rect(grid_coordinate.x(), grid_coordinate.y(), - grid_coordinate.x(), - grid_coordinate.y())); + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1)); rr_graph.set_node_class_num(node, iclass); rr_graph.set_node_capacity(node, 1);