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fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs

This commit is contained in:
tangxifan 2020-03-22 16:11:00 -06:00
parent fdf6a6bd3e
commit ff474d87de
3 changed files with 9 additions and 9 deletions
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1
openfpga/src/annotation/device_rr_gsb.cpp
View File

@ -267,6 +267,7 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraph& rr_graph) {
break;
}
}
/* Add to list if this is a unique mirror*/
if (true == is_unique_module) {
sb_unique_module_.push_back(sb_coordinate);

2
openfpga/src/base/openfpga_build_fabric.cpp
View File

@ -45,7 +45,7 @@ void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx,
"Detected %lu unique switch blocks from a total of %d (compression rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(),
find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()),
100. * (find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - 1));
100. * (find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - 1.));
VTR_LOG("Detected %lu unique general switch blocks from a total of %d (compression rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),

15
vpr/src/tileable_rr_graph/rr_gsb.cpp
View File

@ -952,8 +952,6 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
const e_side& node_side,
const size_t& track_id) const {
/* Ensure rr_nodes are either the output of short-connection or multiplexer */
RRNodeId node = this->get_chan_node(node_side, track_id);
RRNodeId cand_node = cand.get_chan_node(node_side, track_id);
bool is_short_conkt = this->is_sb_node_passing_wire(rr_graph, node_side, track_id);
if (is_short_conkt != cand.is_sb_node_passing_wire(rr_graph, node_side, track_id)) {
@ -968,14 +966,15 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
return true;
}
/* For non-passing wires, check driving rr_nodes */
if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) {
return false;
}
/* Use unsorted/sorted edges */
std::vector<RREdgeId> node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id);
std::vector<RREdgeId> cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id);
/* For non-passing wires, check driving rr_nodes */
if (node_in_edges.size() != cand_node_in_edges.size()) {
return false;
}
VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {
@ -984,7 +983,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
RRNodeId src_node = rr_graph.edge_src_node(src_edge);
RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge);
/* node type should be the same */
if (rr_graph.node_type(src_node) != rr_graph.node_type(cand_node)) {
if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) {
return false;
}
/* switch type should be the same */