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OpenFPGA
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start verification and bug fixing

This commit is contained in:
tangxifan 2020-02-28 14:29:01 -07:00
parent 542fadaaae
commit 80bb2baae5
8 changed files with 37 additions and 10 deletions
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6
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -183,6 +183,12 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
fp << std::endl;
}
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_preconfig_top_testbench()) {
print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
fp << std::endl;
}

1
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -228,6 +228,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
clock_port);
print_verilog_testbench_random_stimuli(fp, atom_ctx,
netlist_annotation,
clock_port_names,
std::string(CHECKFLAG_PORT_POSTFIX),
clock_port);

14
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -5,6 +5,7 @@
* Note: please try to avoid using global variables in this file
* so that we can make it free to use anywhere
*******************************************************************/
#include <algorithm>
#include <iomanip>
/* Headers from vtrutil library */
@ -422,6 +423,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
void print_verilog_testbench_random_stimuli(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& check_flag_port_postfix,
const BasicPort& clock_port) {
/* Validate the file stream */
@ -444,6 +446,11 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
block_name = netlist_annotation.block_name(atom_blk);
}
/* Bypass clock ports */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
continue;
}
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << block_name << " <= 1'b0;" << std::endl;
@ -510,8 +517,13 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
block_name = netlist_annotation.block_name(atom_blk);
}
/* Bypass clock ports */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
continue;
}
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) {
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << block_name << " <= $random;" << std::endl;
}
}

1
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -76,6 +76,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
void print_verilog_testbench_random_stimuli(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& check_flag_port_postfix,
const BasicPort& clock_port);

1
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -855,6 +855,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Add stimuli for reset, set, clock and iopad signals */
print_verilog_testbench_random_stimuli(fp, atom_ctx,
netlist_annotation,
clock_port_names,
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1));

4
openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
View File

@ -168,11 +168,11 @@
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>

2
openfpga/test_script/s298_k6_frac.openfpga
View File

@ -1,5 +1,5 @@
# Run VPR for the s298 design
vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph example_rr_graph.xml
vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
# Read OpenFPGA architecture definition
read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml

18
openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
View File

@ -45,19 +45,22 @@
</model>
</models>
<tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
@ -145,7 +148,10 @@
<pb_type name="io">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation
-->