start verification and bug fixing
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@ -183,6 +183,12 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
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/* To enable pre-configured FPGA simulation */
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if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
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print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
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fp << std::endl;
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}
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/* To enable pre-configured FPGA simulation */
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if (true == verilog_testbench_opts.print_preconfig_top_testbench()) {
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print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
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fp << std::endl;
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}
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@ -228,6 +228,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
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clock_port);
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print_verilog_testbench_random_stimuli(fp, atom_ctx,
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netlist_annotation,
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clock_port_names,
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std::string(CHECKFLAG_PORT_POSTFIX),
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clock_port);
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@ -5,6 +5,7 @@
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* Note: please try to avoid using global variables in this file
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* so that we can make it free to use anywhere
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*******************************************************************/
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#include <algorithm>
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#include <iomanip>
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/* Headers from vtrutil library */
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@ -422,6 +423,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
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void print_verilog_testbench_random_stimuli(std::fstream& fp,
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const AtomContext& atom_ctx,
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const VprNetlistAnnotation& netlist_annotation,
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const std::vector<std::string>& clock_port_names,
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const std::string& check_flag_port_postfix,
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const BasicPort& clock_port) {
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/* Validate the file stream */
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@ -444,6 +446,11 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
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block_name = netlist_annotation.block_name(atom_blk);
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}
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/* Bypass clock ports */
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if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
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continue;
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}
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/* TODO: find the clock inputs will be initialized later */
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if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
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fp << "\t\t" << block_name << " <= 1'b0;" << std::endl;
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@ -510,8 +517,13 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
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block_name = netlist_annotation.block_name(atom_blk);
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}
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/* Bypass clock ports */
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if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
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continue;
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}
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/* TODO: find the clock inputs will be initialized later */
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if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) {
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if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
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fp << "\t\t" << block_name << " <= $random;" << std::endl;
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}
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}
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@ -76,6 +76,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
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void print_verilog_testbench_random_stimuli(std::fstream& fp,
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const AtomContext& atom_ctx,
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const VprNetlistAnnotation& netlist_annotation,
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const std::vector<std::string>& clock_port_names,
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const std::string& check_flag_port_postfix,
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const BasicPort& clock_port);
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@ -855,6 +855,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
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/* Add stimuli for reset, set, clock and iopad signals */
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print_verilog_testbench_random_stimuli(fp, atom_ctx,
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netlist_annotation,
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clock_port_names,
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std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
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BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1));
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@ -168,11 +168,11 @@
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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@ -1,5 +1,5 @@
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# Run VPR for the s298 design
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vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph example_rr_graph.xml
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vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
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@ -45,19 +45,22 @@
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</model>
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</models>
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<tiles>
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<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
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If you need to register the I/O, define clocks in the circuit models
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These clocks can be handled in back-end
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-->
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<tile name="io" capacity="8" area="0">
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<equivalent_sites>
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<site pb_type="io"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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<loc side="left">io.outpad io.inpad</loc>
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<loc side="top">io.outpad io.inpad</loc>
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<loc side="right">io.outpad io.inpad</loc>
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<loc side="bottom">io.outpad io.inpad</loc>
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</pinlocations>
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</tile>
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<tile name="clb" area="53894">
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@ -145,7 +148,10 @@
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
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If you need to register the I/O, define clocks in the circuit models
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These clocks can be handled in back-end
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-->
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<!-- A mode denotes the physical implementation of an I/O
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This mode will be not packable but is mainly used for fabric verilog generation
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-->
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