start improve fabric bitstream database to support frame-based configuration protocol

openfpga/src/fpga_bitstream/fabric_bitstream.cpp

@@ -0,0 +1,77 @@
+/******************************************************************************
+ * This file includes member functions for data structure FabricBitstream
+ ******************************************************************************/
+#include <algorithm>
+
+#include "vtr_assert.h"
+#include "fabric_bitstream.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors : Aggregates
+ *************************************************/
+/* Find all the configuration bits */
+FabricBitstream::fabric_bit_range FabricBitstream::bits() const {
+  return vtr::make_range(bit_ids_.begin(), bit_ids_.end());
+}
+
+/******************************************************************************
+ * Public Accessors
+ ******************************************************************************/
+ConfigBitId FabricBitstream::config_bit(const FabricBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return config_bit_ids_[bit_id];
+}
+
+std::vector<bool> FabricBitstream::bit_address(const FabricBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_addresses_[bit_id];
+}
+
+bool FabricBitstream::bit_din(const FabricBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_dins_[bit_id];
+}
+
+/******************************************************************************
+ * Public Mutators
+ ******************************************************************************/
+FabricBitId FabricBitstream::add_bit(const ConfigBitId& config_bit_id) {
+  FabricBitId bit = FabricBitId(bit_ids_.size());
+  /* Add a new bit, and allocate associated data structures */
+  bit_ids_.push_back(bit);
+  config_bit_ids_.push_back(config_bit_id);
+  bit_addresses_.emplace_back();
+  bit_dins_.push_back(false);
+
+  return bit; 
+}
+
+void FabricBitstream::set_bit_address(const FabricBitId& bit_id,
+                                             const std::vector<bool>& address) {
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+  bit_addresses_[bit_id] = address;
+}
+
+void FabricBitstream::set_bit_din(const FabricBitId& bit_id,
+                                         const bool& din) {
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+  bit_dins_[bit_id] = din;
+}
+
+/******************************************************************************
+ * Public Validators
+ ******************************************************************************/
+bool FabricBitstream::valid_bit_id(const FabricBitId& bit_id) const {
+  return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]);
+}
+
+} /* end namespace openfpga */

openfpga/src/fpga_bitstream/fabric_bitstream.h

@@ -0,0 +1,90 @@
+/******************************************************************************
+ * This file introduces a data structure to store fabric-dependent bitstream information 
+ *
+ * General concept
+ * ---------------
+ * The idea is to create a unified data structure that stores the sequence of configuration 
+ * bit in the architecture bitstream database
+ * as well as the information (such as address of each bit) required by a specific 
+ * configuration protocol
+ *
+ * Cross-reference 
+ * ---------------
+ * By using the link between ArchBitstreamManager and FabricBitstream, 
+ * we can build a sequence of configuration bits to fit different configuration protocols.
+ *
+ *     +----------------------+                 +--------------------------+
+ *     |                      |   ConfigBitId   |                          |
+ *     | ArchBitstreamManager |---------------->|  FabricBitstream  |
+ *     |                      |                 |                          |   
+ *     +----------------------+                 +--------------------------+ 
+ *
+ * Restrictions:
+ * 1. Each block inside BitstreamManager should have only 1 parent block 
+ *    and multiple child block
+ * 2. Each bit inside BitstreamManager should have only 1 parent block 
+ * 
+ ******************************************************************************/
+#ifndef FABRIC_BITSTREAM_H
+#define FABRIC_BITSTREAM_H
+
+#include <vector>
+#include "vtr_vector.h"
+
+#include "bitstream_manager_fwd.h"
+#include "fabric_bitstream_fwd.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class FabricBitstream {
+  public: /* Types and ranges */
+    typedef vtr::vector<FabricBitId, FabricBitId>::const_iterator fabric_bit_iterator;
+
+    typedef vtr::Range<fabric_bit_iterator> fabric_bit_range;
+
+  public: /* Public aggregators */
+    /* Find all the configuration bits */
+    fabric_bit_range bits() const;
+
+  public:  /* Public Accessors */
+    /* Find the configuration bit id in architecture bitstream database */
+    ConfigBitId config_bit(const FabricBitId& bit_id) const;
+
+    /* Find the address of bitstream */
+    std::vector<bool> bit_address(const FabricBitId& bit_id) const;
+
+    /* Find the data-in of bitstream */
+    bool bit_din(const FabricBitId& bit_id) const;
+
+  public:  /* Public Mutators */
+    /* Add a new configuration bit to the bitstream manager */
+    FabricBitId add_bit(const ConfigBitId& config_bit_id);
+
+    void set_bit_address(const FabricBitId& bit_id,
+                         const std::vector<bool>& address);
+
+    void set_bit_din(const FabricBitId& bit_id,
+                     const bool& din);
+
+  public:  /* Public Validators */
+    bool valid_bit_id(const FabricBitId& bit_id) const;
+
+  private: /* Internal data */
+    /* Unique id of a bit in the Bitstream */
+    vtr::vector<FabricBitId, FabricBitId> bit_ids_; 
+    vtr::vector<FabricBitId, ConfigBitId> config_bit_ids_; 
+
+    /* Address bits: this is designed for memory decoders
+     * Here we store the binary format of the address, which can be loaded
+     * to the configuration protocol directly 
+     */
+    vtr::vector<FabricBitId, std::vector<bool>> bit_addresses_;
+
+    /* Data input (Din) bits: this is designed for memory decoders */
+    vtr::vector<FabricBitId, bool> bit_dins_;
+};
+
+} /* end namespace openfpga */
+
+#endif

openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h

@@ -0,0 +1,23 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for fabric-dependent bitstream database
+ * Please refer to fabric_bitstream.h for more details
+ *************************************************/
+#ifndef FABRIC_BITSTREAM_FWD_H
+#define FABRIC_BITSTREAM_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for BitstreamContext */
+struct fabric_bit_id_tag;
+
+typedef vtr::StrongId<fabric_bit_id_tag> FabricBitId;
+
+class FabricBitstream;
+
+} /* end namespace openfpga */
+
+#endif