add architecture decoder (for frame-based config memory) to Verilog writer
This commit is contained in:
tangxifan
parent
c696e3d20f
commit
5c5a044c68
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@ -48,6 +48,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
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openfpga_ctx.mutable_verilog_netlists(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.mux_lib(),
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openfpga_ctx.decoder_lib(),
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g_vpr_ctx.device(),
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.device_rr_gsb(),
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@ -54,6 +54,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const DecoderLibrary& decoder_lib,
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const DeviceContext& device_ctx,
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const VprDeviceAnnotation& device_annotation,
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const DeviceRRGSB& device_rr_gsb,
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@ -90,7 +91,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
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* Without the modules in the module manager, core logic generation is not possible!!!
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*/
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print_verilog_submodule(module_manager, netlist_manager,
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mux_lib, circuit_lib,
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mux_lib, decoder_lib, circuit_lib,
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submodule_dir_path,
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options);
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@ -8,6 +8,7 @@
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#include <string>
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#include <vector>
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#include "mux_library.h"
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#include "decoder_library.h"
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#include "circuit_library.h"
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#include "vpr_context.h"
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#include "vpr_device_annotation.h"
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@ -32,6 +33,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const DecoderLibrary& decoder_lib,
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const DeviceContext& device_ctx,
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const VprDeviceAnnotation& device_annotation,
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const DeviceRRGSB& device_rr_gsb,
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@ -37,6 +37,7 @@ constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";
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constexpr char* ROUTING_VERILOG_FILE_NAME = "routing.v";
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constexpr char* MUXES_VERILOG_FILE_NAME = "muxes.v";
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constexpr char* LOCAL_ENCODER_VERILOG_FILE_NAME = "local_encoder.v";
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constexpr char* ARCH_ENCODER_VERILOG_FILE_NAME = "arch_encoder.v";
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constexpr char* MEMORIES_VERILOG_FILE_NAME = "memories.v";
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constexpr char* WIRES_VERILOG_FILE_NAME = "wires.v";
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constexpr char* ESSENTIALS_VERILOG_FILE_NAME = "inv_buf_passgate.v";
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@ -1,7 +1,6 @@
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/***************************************************************************************
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* This file includes functions to generate Verilog modules of decoders
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***************************************************************************************/
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/* TODO: merge verilog_decoder.c to this source file and rename to verilog_decoder.cpp */
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#include <string>
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/* Headers from vtrutil library */
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@ -15,6 +14,7 @@
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#include "decoder_library_utils.h"
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#include "module_manager.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "verilog_constants.h"
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@ -133,7 +133,6 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
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print_verilog_module_end(fp, module_name);
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}
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/***************************************************************************************
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* This function will generate all the unique Verilog modules of local decoders for
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* the multiplexers used in a FPGA fabric
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@ -227,4 +226,179 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
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VTR_LOG("Done\n");
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}
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/***************************************************************************************
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* Create a Verilog module for a decoder used as a configuration protocol
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* in FPGA architecture
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*
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* Address
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* | | ... |
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* v v v
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* +-----------+
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* Enable->/ \
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* / Decoder \
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* +-----------------+
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* | | | ... | | |
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* v v v v v v
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* Data output
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*
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* The outputs are assumes to be one-hot codes (at most only one '1' exist)
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* Considering this fact, there are only num_of_outputs conditions to be encoded.
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* Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
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*
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* The decoder has an enable signal which is active at logic '1'.
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* When activated, the decoder will output decoding results to the data output port
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* Otherwise, the data output port will be always all-zero
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***************************************************************************************/
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static
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void print_verilog_arch_decoder_module(std::fstream& fp,
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const ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder) {
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/* Get the number of inputs */
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size_t addr_size = decoder_lib.addr_size(decoder);
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size_t data_size = decoder_lib.data_size(decoder);
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/* Validate the FILE handler */
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VTR_ASSERT(true == valid_file_stream(fp));
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/* Create a name for the decoder */
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std::string module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.find_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* Find module ports */
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/* Enable port */
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ModulePortId enable_port_id = module_manager.find_module_port(module_id, std::string(DECODER_ENABLE_PORT_NAME));
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BasicPort enable_port = module_manager.module_port(module_id, enable_port_id);
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/* Address port */
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ModulePortId addr_port_id = module_manager.find_module_port(module_id, std::string(DECODER_ADDRESS_PORT_NAME));
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BasicPort addr_port = module_manager.module_port(module_id, addr_port_id);
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/* Find each output port */
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ModulePortId data_port_id = module_manager.find_module_port(module_id, std::string(DECODER_DATA_OUT_PORT_NAME));
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BasicPort data_port = module_manager.module_port(module_id, data_port_id);
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/* Data port is registered. It should be outputted as
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* output reg [lsb:msb] data
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*/
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BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
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if (true == decoder_lib.use_data_inv_port(decoder)) {
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ModulePortId data_inv_port_id = module_manager.find_module_port(module_id, std::string(DECODER_DATA_OUT_INV_PORT_NAME));
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data_inv_port = module_manager.module_port(module_id, data_inv_port_id);
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}
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/* dump module definition + ports */
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print_verilog_module_declaration(fp, module_manager, module_id);
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/* Finish dumping ports */
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print_verilog_comment(fp, std::string("----- BEGIN Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
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/* Print the truth table of this decoder */
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/* Internal logics */
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/* Early exit: Corner case for data size = 1 the logic is very simple:
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* data = addr;
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* data_inv = ~data_inv
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*/
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if (1 == data_size) {
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print_verilog_wire_connection(fp, data_port, addr_port, false);
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/* Depend on if the inverted data output port is needed or not */
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if (true == decoder_lib.use_data_inv_port(decoder)) {
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print_verilog_wire_connection(fp, data_inv_port, addr_port, true);
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}
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print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, module_name);
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return;
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}
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/* We use a magic number -1 as the addr=1 should be mapped to ...1
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* Otherwise addr will map addr=1 to ..10
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* Note that there should be a range for the shift operators
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* We should narrow the encoding to be applied to a given set of data
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* This will lead to that any addr which falls out of the op code of data
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* will give a all-zero code
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* For example:
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* data is 5-bit while addr is 3-bit
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* data=8'b0_0000 will be encoded to addr=3'b001;
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* data=8'b0_0001 will be encoded to addr=3'b010;
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* data=8'b0_0010 will be encoded to addr=3'b011;
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* data=8'b0_0100 will be encoded to addr=3'b100;
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* data=8'b0_1000 will be encoded to addr=3'b101;
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* data=8'b1_0000 will be encoded to addr=3'b110;
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* The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
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*/
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fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
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fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << "1'b1) begin" << std::endl;
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fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
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/* Create a string for addr and data */
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for (size_t i = 0; i < data_size; ++i) {
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fp << "\t\t\t" << generate_verilog_constant_values(itobin_vec(i, addr_size));
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fp << " : ";
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fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(i, data_size));
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fp << ";" << std::endl;
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}
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fp << "\t\t\t" << "default : ";
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fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size - 1, data_size));
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fp << ";" << std::endl;
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fp << "\t\t" << "endcase" << std::endl;
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fp << "\t" << "end" << std::endl;
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if (true == decoder_lib.use_data_inv_port(decoder)) {
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print_verilog_wire_connection(fp, data_inv_port, data_port, true);
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}
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print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, module_name);
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}
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/***************************************************************************************
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* This function will generate all the unique Verilog modules of decoders for
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* configuration protocols in a FPGA fabric
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* It will generate these decoder Verilog modules using behavioral description.
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* Note that the implementation of local decoders can be dependent on the technology
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* and standard cell libraries.
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* Therefore, behavioral Verilog is used and the local decoders should be synthesized
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* before running the back-end flow for FPGA fabric
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* See more details in the function print_verilog_arch_decoder() for more details
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***************************************************************************************/
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void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const DecoderLibrary& decoder_lib,
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const std::string& submodule_dir) {
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std::string verilog_fname(submodule_dir + std::string(ARCH_ENCODER_VERILOG_FILE_NAME));
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(verilog_fname.c_str(), fp);
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/* Print out debugging information for if the file is not opened/created properly */
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VTR_LOG("Writing Verilog netlist for configuration decoders '%s'...",
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verilog_fname.c_str());
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print_verilog_file_header(fp, "Decoders for fabric configuration protocol ");
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/* Generate Verilog modules for the found unique local encoders */
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for (const auto& decoder : decoder_lib.decoders()) {
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print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder);
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}
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/* Close the file stream */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
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VTR_LOG("Done\n");
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}
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} /* end namespace openfpga */
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@ -11,6 +11,7 @@
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#include "circuit_library.h"
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#include "mux_graph.h"
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#include "mux_library.h"
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#include "decoder_library.h"
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#include "module_manager.h"
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#include "netlist_manager.h"
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@ -27,6 +28,12 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
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const CircuitLibrary& circuit_lib,
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const std::string& submodule_dir);
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void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const DecoderLibrary& decoder_lib,
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const std::string& submodule_dir);
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} /* end namespace openfpga */
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#endif
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@ -34,6 +34,7 @@ namespace openfpga {
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void print_verilog_submodule(ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const MuxLibrary& mux_lib,
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const DecoderLibrary& decoder_lib,
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const CircuitLibrary& circuit_lib,
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const std::string& submodule_dir,
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const FabricVerilogOption& fpga_verilog_opts) {
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@ -49,6 +50,12 @@ void print_verilog_submodule(ModuleManager& module_manager,
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submodule_dir,
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circuit_lib);
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/* Decoders for architecture */
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print_verilog_submodule_arch_decoders(const_cast<const ModuleManager&>(module_manager),
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netlist_manager,
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decoder_lib,
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submodule_dir);
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/* Routing multiplexers */
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/* NOTE: local decoders generation must go before the MUX generation!!!
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* because local decoders modules will be instanciated in the MUX modules
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@ -7,6 +7,7 @@
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#include "module_manager.h"
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#include "netlist_manager.h"
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#include "mux_library.h"
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#include "decoder_library.h"
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#include "fabric_verilog_options.h"
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/********************************************************************
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@ -19,6 +20,7 @@ namespace openfpga {
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void print_verilog_submodule(ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const MuxLibrary& mux_lib,
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const DecoderLibrary& decoder_lib,
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const CircuitLibrary& circuit_lib,
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const std::string& submodule_dir,
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const FabricVerilogOption& fpga_verilog_opts);
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