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OpenFPGA
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer

This commit is contained in:
tangxifan 2020-03-03 12:29:58 -07:00
parent 3241d8bd37
commit 7fcd27e000
6 changed files with 43 additions and 3 deletions
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13
openfpga/src/base/openfpga_naming.cpp
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@ -17,6 +17,19 @@
/* begin namespace openfpga */
namespace openfpga {
/************************************************
* A generic function to generate the instance name
* in the following format:
* <instance_name>_<id>_
* This is mainly used by module manager to give a default
* name for each instance when outputting the module
* in Verilog/SPICE format
***********************************************/
std::string generate_instance_name(const std::string& instance_name,
const size_t& instance_id) {
return instance_name + std::string("_") + std::to_string(instance_id) + std::string("_");
}
/************************************************
* Generate the node name for a multiplexing structure
* Case 1 : If there is an intermediate buffer followed by,

3
openfpga/src/base/openfpga_naming.h
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@ -23,6 +23,9 @@
/* begin namespace openfpga */
namespace openfpga {
std::string generate_instance_name(const std::string& instance_name,
const size_t& instance_id);
std::string generate_mux_node_name(const size_t& node_level,
const bool& add_buffer_postfix);

6
openfpga/src/fabric/build_grid_modules.cpp
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@ -428,6 +428,12 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager,
size_t wire_instance = module_manager.num_instance(pb_module, wire_module);
module_manager.add_child_module(pb_module, wire_module);
/* Give an instance name: this name should be consistent with the block name given in SDC generator,
* If you want to bind the SDC generation to modules
*/
std::string wire_instance_name = generate_instance_name(module_manager.module_name(wire_module), wire_instance);
module_manager.set_child_instance_name(pb_module, wire_module, wire_instance, wire_instance_name);
/* Ensure input and output ports of the wire model has only 1 pin respectively */
VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0]));
VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0]));

16
openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
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@ -47,6 +47,10 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
/* Disable all the ports of current module (parent_module)!
* Hierarchy name already includes the instance name of parent_module
*/
fp << "#######################################" << std::endl;
fp << "# Disable all the ports for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
fp << "#######################################" << std::endl;
fp << "set_disable_timing ";
fp << hierarchy_name;
fp << "*";
@ -76,7 +80,7 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, hierarchy_name,
rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, updated_hierarchy_name,
&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]));
}
}
@ -135,6 +139,10 @@ void disable_pb_graph_node_unused_pins(std::fstream& fp,
const PhysicalPbId& pb_id = physical_pb.find_pb(physical_pb_graph_node);
VTR_ASSERT(true == physical_pb.valid_pb_id(pb_id));
fp << "#######################################" << std::endl;
fp << "# Disable unused pins for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
fp << "#######################################" << std::endl;
/* Disable unused input pins */
for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
@ -180,6 +188,10 @@ void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp,
t_pb_graph_node* physical_pb_graph_node,
const PhysicalPb& physical_pb) {
fp << "#######################################" << std::endl;
fp << "# Disable unused mux_inputs for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
fp << "#######################################" << std::endl;
t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
@ -409,7 +421,7 @@ void rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(std::fstream&
std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, device_annotation,
module_manager, child_module, hierarchy_name,
module_manager, child_module, updated_hierarchy_name,
&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]),
physical_pb);
}

4
openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
View File

@ -98,6 +98,8 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
VTR_ASSERT(!sink_instance_name.empty());
/* Get the input id that is used! Disable the unused inputs! */
fp << "set_disable_timing ";
fp << parent_instance_name;
@ -221,6 +223,8 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
VTR_ASSERT(!sink_instance_name.empty());
/* Get the input id that is used! Disable the unused inputs! */
fp << "set_disable_timing ";
fp << parent_instance_name;

4
openfpga/src/fpga_verilog/verilog_module_writer.cpp
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@ -16,6 +16,8 @@
#include "openfpga_port.h"
#include "openfpga_digest.h"
#include "openfpga_naming.h"
#include "module_manager_utils.h"
#include "verilog_port_types.h"
#include "verilog_writer_utils.h"
@ -371,7 +373,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
* if not, we use a default name <name>_<num_instance_in_parent_module>
*/
if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) {
fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl;
fp << generate_instance_name(module_manager.module_name(child_module), instance_id) << " (" << std::endl;
} else {
fp << module_manager.instance_name(parent_module, child_module, instance_id) << " (" << std::endl;
}