now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
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@ -17,6 +17,19 @@
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/* begin namespace openfpga */
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namespace openfpga {
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/************************************************
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* A generic function to generate the instance name
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* in the following format:
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* <instance_name>_<id>_
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* This is mainly used by module manager to give a default
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* name for each instance when outputting the module
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* in Verilog/SPICE format
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***********************************************/
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std::string generate_instance_name(const std::string& instance_name,
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const size_t& instance_id) {
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return instance_name + std::string("_") + std::to_string(instance_id) + std::string("_");
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}
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/************************************************
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* Generate the node name for a multiplexing structure
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* Case 1 : If there is an intermediate buffer followed by,
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@ -23,6 +23,9 @@
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/* begin namespace openfpga */
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namespace openfpga {
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std::string generate_instance_name(const std::string& instance_name,
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const size_t& instance_id);
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std::string generate_mux_node_name(const size_t& node_level,
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const bool& add_buffer_postfix);
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@ -428,6 +428,12 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager,
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size_t wire_instance = module_manager.num_instance(pb_module, wire_module);
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module_manager.add_child_module(pb_module, wire_module);
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/* Give an instance name: this name should be consistent with the block name given in SDC generator,
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* If you want to bind the SDC generation to modules
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*/
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std::string wire_instance_name = generate_instance_name(module_manager.module_name(wire_module), wire_instance);
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module_manager.set_child_instance_name(pb_module, wire_module, wire_instance, wire_instance_name);
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/* Ensure input and output ports of the wire model has only 1 pin respectively */
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VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0]));
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VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0]));
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@ -47,6 +47,10 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
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/* Disable all the ports of current module (parent_module)!
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* Hierarchy name already includes the instance name of parent_module
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*/
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fp << "#######################################" << std::endl;
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fp << "# Disable all the ports for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
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fp << "#######################################" << std::endl;
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fp << "set_disable_timing ";
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fp << hierarchy_name;
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fp << "*";
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@ -76,7 +80,7 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
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std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
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rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, hierarchy_name,
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rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, updated_hierarchy_name,
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&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]));
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}
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}
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@ -135,6 +139,10 @@ void disable_pb_graph_node_unused_pins(std::fstream& fp,
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const PhysicalPbId& pb_id = physical_pb.find_pb(physical_pb_graph_node);
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VTR_ASSERT(true == physical_pb.valid_pb_id(pb_id));
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fp << "#######################################" << std::endl;
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fp << "# Disable unused pins for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
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fp << "#######################################" << std::endl;
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/* Disable unused input pins */
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for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
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@ -180,6 +188,10 @@ void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp,
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t_pb_graph_node* physical_pb_graph_node,
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const PhysicalPb& physical_pb) {
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fp << "#######################################" << std::endl;
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fp << "# Disable unused mux_inputs for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
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fp << "#######################################" << std::endl;
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t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
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t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
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@ -409,7 +421,7 @@ void rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(std::fstream&
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std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
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rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, device_annotation,
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module_manager, child_module, hierarchy_name,
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module_manager, child_module, updated_hierarchy_name,
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&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]),
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physical_pb);
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}
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@ -98,6 +98,8 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
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BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
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sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
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module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
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VTR_ASSERT(!sink_instance_name.empty());
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/* Get the input id that is used! Disable the unused inputs! */
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fp << "set_disable_timing ";
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fp << parent_instance_name;
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@ -221,6 +223,8 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
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BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
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sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
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module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
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VTR_ASSERT(!sink_instance_name.empty());
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/* Get the input id that is used! Disable the unused inputs! */
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fp << "set_disable_timing ";
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fp << parent_instance_name;
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@ -16,6 +16,8 @@
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "module_manager_utils.h"
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#include "verilog_port_types.h"
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#include "verilog_writer_utils.h"
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@ -371,7 +373,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
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* if not, we use a default name <name>_<num_instance_in_parent_module>
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*/
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if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) {
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fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl;
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fp << generate_instance_name(module_manager.module_name(child_module), instance_id) << " (" << std::endl;
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} else {
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fp << module_manager.instance_name(parent_module, child_module, instance_id) << " (" << std::endl;
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}
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