adapt PnR SDC writer
This commit is contained in:
tangxifan
parent
89c51b70e3
commit
e45fa18c4c
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/********************************************************************
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* This file includes functions that print SDC (Synopsys Design Constraint)
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* files in physical design tools, i.e., Place & Route (PnR) tools
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* The SDC files are used to constrain the physical design for each module
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* in FPGA fabric, such as Configurable Logic Blocks (CLBs),
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* Heterogeneous blocks, Switch Blocks (SBs) and Connection Blocks (CBs)
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*
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* Note that this is different from the SDC to constrain VPR Place&Route
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* engine! These SDCs are designed for PnR to generate FPGA layouts!!!
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*******************************************************************/
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#include <ctime>
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#include <fstream>
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#include <iomanip>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_time.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "mux_utils.h"
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#include "openfpga_naming.h"
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#include "sdc_writer_naming.h"
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#include "sdc_writer_utils.h"
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#include "sdc_memory_utils.h"
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#include "pnr_sdc_routing_writer.h"
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#include "pnr_sdc_grid_writer.h"
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#include "pnr_sdc_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Local variables
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*******************************************************************/
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constexpr float SDC_FIXED_PROG_CLOCK_PERIOD = 100;
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constexpr float SDC_FIXED_CLOCK_PERIOD = 10;
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/********************************************************************
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* Print a SDC file to constrain the global ports of FPGA fabric
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* in particular clock ports
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*
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* For programming clock, we give a fixed period, while for operating
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* clock, we constrain with critical path delay
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*******************************************************************/
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static
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void print_pnr_sdc_global_ports(const std::string& sdc_dir,
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const float& critical_path_delay,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitPortId>& global_ports) {
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/* Create the file name for Verilog netlist */
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std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(sdc_fname.c_str(), fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Clock contraints for PnR"));
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/* Get clock port from the global port */
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for (const CircuitPortId& clock_port : global_ports) {
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if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
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continue;
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}
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/* Reach here, it means a clock port and we need print constraints */
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float clock_period = critical_path_delay;
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/* For programming clock, we give a fixed period */
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if (true == circuit_lib.port_is_prog(clock_port)) {
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clock_period = SDC_FIXED_PROG_CLOCK_PERIOD;
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Create programmable clock " << std::endl;
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fp << "##################################################" << std::endl;
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} else {
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Create clock " << std::endl;
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fp << "##################################################" << std::endl;
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}
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for (const size_t& pin : circuit_lib.pins(clock_port)) {
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BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin);
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fp << "create_clock ";
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fp << generate_sdc_port(port_to_constrain) << "-period ";
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fp << std::setprecision(10) << clock_period;
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fp << " -waveform {0 ";
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fp << std::setprecision(10) << clock_period / 2;
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fp << "}" << std::endl;
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fp << std::endl;
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}
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}
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/* For non-clock port from the global port: give a fixed period */
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for (const CircuitPortId& global_port : global_ports) {
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if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) {
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continue;
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}
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Constrain other global ports " << std::endl;
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fp << "##################################################" << std::endl;
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/* Reach here, it means a non-clock global port and we need print constraints */
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float clock_period = SDC_FIXED_CLOCK_PERIOD;
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for (const size_t& pin : circuit_lib.pins(global_port)) {
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BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
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fp << "create_clock ";
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fp << generate_sdc_port(port_to_constrain) << "-period ";
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fp << std::setprecision(10) << clock_period;
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fp << " -waveform {0 ";
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fp << std::setprecision(10) << clock_period / 2;
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fp << "} ";
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fp << "[list [get_ports { " << generate_sdc_port(port_to_constrain) << "}]]" << std::endl;
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fp << "set_drive 0 " << generate_sdc_port(port_to_constrain) << std::endl;
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fp << std::endl;
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}
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}
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Break combinational loops in FPGA fabric, which mainly come from
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* configurable memory cells.
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* To handle this, we disable the outputs of memory cells
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const ModuleId& top_module) {
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/* Create the file name for Verilog netlist */
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable configurable memory outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(sdc_fname.c_str(), fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Disable configurable memory outputs for PnR"));
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/* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */
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rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, top_module,
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format_dir_path(module_manager.module_name(top_module)));
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Break combinational loops in FPGA fabric, which mainly come from
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* loops of multiplexers.
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* To handle this, we disable the timing at outputs of routing multiplexers
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*******************************************************************/
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static
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void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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const ModuleManager& module_manager) {
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/* Create the file name for Verilog netlist */
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(sdc_fname.c_str(), fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR"));
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/* Iterate over the MUX modules */
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for (const MuxId& mux_id : mux_lib.muxes()) {
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const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id);
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/* Skip LUTs, we only care about multiplexers here */
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if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
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continue;
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}
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const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id);
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std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model,
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find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()),
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std::string(""));
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/* Find the module name in module manager */
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ModuleId mux_module = module_manager.find_module(mux_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
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/* Disable the timing for the output ports */
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for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) {
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fp << "set_disable_timing [get_pins -filter \"name =~ " << output_port.get_name() << "*\" ";
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fp << "-of [get_cells -hier -filter \"ref_lib_cell_name == " << mux_module_name << "\"]]" << std::endl;
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fp << std::endl;
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}
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}
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Break combinational loops in FPGA fabric, which mainly come from
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* loops of multiplexers.
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* To handle this, we disable the timing at outputs of Switch blocks
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* This function is designed for flatten routing hierarchy
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*******************************************************************/
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static
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void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const DeviceRRGSB& device_rr_gsb) {
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/* Create the file name for Verilog netlist */
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(sdc_fname.c_str(), fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
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/* Get the range of SB array */
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vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
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/* Go for each SB */
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for (size_t ix = 0; ix < sb_range.x(); ++ix) {
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for (size_t iy = 0; iy < sb_range.y(); ++iy) {
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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if (false == rr_gsb.is_sb_exist()) {
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continue;
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}
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate);
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ModuleId sb_module = module_manager.find_module(sb_instance_name);
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Disable the outputs of the module */
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for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) {
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fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl;
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fp << std::endl;
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}
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}
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}
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Break combinational loops in FPGA fabric, which mainly come from
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* loops of multiplexers.
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* To handle this, we disable the timing at outputs of Switch blocks
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* This function is designed for compact routing hierarchy
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*******************************************************************/
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static
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void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const ModuleId& top_module,
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const DeviceRRGSB& device_rr_gsb) {
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/* Create the file name for Verilog netlist */
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(sdc_fname.c_str(), fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
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/* Build unique switch block modules */
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for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
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const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate);
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ModuleId sb_module = module_manager.find_module(sb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Find all the instances in the top-level module */
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for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
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std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
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/* Disable the outputs of the module */
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for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) {
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fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl;
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fp << std::endl;
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}
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}
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}
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Top-level function to print a number of SDC files in different purpose
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* This function will generate files upon the options provided by users
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* 1. Design constraints for CLBs
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* 2. Design constraints for Switch Blocks
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* 3. Design constraints for Connection Blocks
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* 4. Design constraints for breaking the combinational loops in FPGA fabric
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*******************************************************************/
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void print_pnr_sdc(const PnrSdcOption& sdc_options,
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const float& critical_path_delay,
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const DeviceContext& device_ctx,
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const VprDeviceAnnotation& device_annotation,
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const DeviceRRGSB& device_rr_gsb,
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const ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitPortId>& global_ports,
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const bool& compact_routing_hierarchy) {
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/* Constrain global ports */
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if (true == sdc_options.constrain_global_port()) {
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print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports);
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}
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Output Design Constraints to disable outputs of memory cells */
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if (true == sdc_options.constrain_configurable_memory_outputs()) {
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print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), module_manager, top_module);
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}
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/* Break loops from Multiplexer Output */
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if (true == sdc_options.constrain_routing_multiplexer_outputs()) {
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print_sdc_disable_routing_multiplexer_outputs(sdc_options.sdc_dir(),
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mux_lib, circuit_lib,
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module_manager);
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}
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/* Break loops from any SB output */
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if (true == sdc_options.constrain_switch_block_outputs()) {
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if (true == compact_routing_hierarchy) {
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print_pnr_sdc_compact_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
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module_manager, top_module,
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device_rr_gsb);
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} else {
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VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
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print_pnr_sdc_flatten_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
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module_manager,
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device_rr_gsb);
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}
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}
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/* Output routing constraints for Switch Blocks */
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if (true == sdc_options.constrain_sb()) {
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if (true == compact_routing_hierarchy) {
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print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(),
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module_manager,
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device_ctx.rr_graph,
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device_rr_gsb);
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} else {
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VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
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print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(),
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module_manager,
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device_ctx.rr_graph,
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device_rr_gsb);
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}
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}
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/* Output routing constraints for Connection Blocks */
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if (true == sdc_options.constrain_cb()) {
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if (true == compact_routing_hierarchy) {
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print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(),
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module_manager,
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device_ctx.rr_graph,
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device_rr_gsb);
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} else {
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VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
|
||||
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(),
|
||||
module_manager,
|
||||
device_ctx.rr_graph,
|
||||
device_rr_gsb);
|
||||
}
|
||||
}
|
||||
|
||||
/* Output Timing constraints for Programmable blocks */
|
||||
if (true == sdc_options.constrain_grid()) {
|
||||
print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(),
|
||||
device_ctx,
|
||||
device_annotation,
|
||||
module_manager);
|
||||
}
|
||||
}
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
#ifndef PNR_SDC_WRITER_H
|
||||
#define PNR_SDC_WRITER_H
|
||||
|
||||
/********************************************************************
|
||||
* Include header files that are required by function declaration
|
||||
*******************************************************************/
|
||||
#include <string>
|
||||
#include <vector>
|
||||
#include "vpr_context.h"
|
||||
#include "vpr_device_annotation.h"
|
||||
#include "device_rr_gsb.h"
|
||||
#include "module_manager.h"
|
||||
#include "mux_library.h"
|
||||
#include "circuit_library.h"
|
||||
#include "pnr_sdc_option.h"
|
||||
|
||||
/********************************************************************
|
||||
* Function declaration
|
||||
*******************************************************************/
|
||||
|
||||
/* begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
void print_pnr_sdc(const PnrSdcOption& sdc_options,
|
||||
const float& critical_path_delay,
|
||||
const DeviceContext& device_ctx,
|
||||
const VprDeviceAnnotation& device_annotation,
|
||||
const DeviceRRGSB& device_rr_gsb,
|
||||
const ModuleManager& module_manager,
|
||||
const MuxLibrary& mux_lib,
|
||||
const CircuitLibrary& circuit_lib,
|
||||
const std::vector<CircuitPortId>& global_ports,
|
||||
const bool& compact_routing_hierarchy);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue