tangxifan
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91627abe12
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[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
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2021-10-30 11:53:46 -07:00 |
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tangxifan
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e9d29e27e5
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[Tool] Bug fix
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2021-07-02 15:32:30 -06:00 |
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tangxifan
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6e6c3e9fa4
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[Tool] Patch the critical bug in the use of signal polarity in pin constraints
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2021-07-02 15:26:21 -06:00 |
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tangxifan
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9074bffa68
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[Tool] Support customized default value in pin constraint file
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2021-07-01 23:43:19 -06:00 |
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tangxifan
|
d0e4f8521f
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[Tool] Bug fix on the reset stimuli
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2021-07-01 19:58:54 -06:00 |
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tangxifan
|
b5df1f9aeb
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[Tool] Bug fix for redundant endif in netlists
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2021-06-29 17:02:16 -06:00 |
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tangxifan
|
b83eef47b4
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[Tool] Bug fix for testbench generation without self checking codes
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2021-06-29 16:27:29 -06:00 |
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tangxifan
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6a260cadbf
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[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
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2021-06-29 15:42:23 -06:00 |
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tangxifan
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7ac7de789e
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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tangxifan
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77dddaeb39
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[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
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2021-06-29 14:26:33 -06:00 |
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tangxifan
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a3208b332b
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[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
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2021-06-29 11:50:53 -06:00 |
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tangxifan
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dfe1db996a
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[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
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2021-06-29 09:56:04 -06:00 |
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tangxifan
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87446a14c3
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[Tool] Bug fix for the option ``--embed_bitstream none``
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2021-06-27 19:45:06 -06:00 |
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tangxifan
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991062e9bf
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[Tool] Bug fix
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2021-06-25 15:22:42 -06:00 |
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tangxifan
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90163fab6c
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[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
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2021-06-25 15:06:07 -06:00 |
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tangxifan
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2bb514c51a
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[Tool] Support time unit in writing simulation information file
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2021-06-25 10:33:29 -06:00 |
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tangxifan
|
bcc16d732c
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[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
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2021-06-25 10:10:16 -06:00 |
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tangxifan
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67dec810eb
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[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
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2021-06-24 17:27:32 -06:00 |
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tangxifan
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549657e1fb
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[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
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2021-06-24 17:13:36 -06:00 |
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tangxifan
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5364d8104f
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[Tool] Add signal_init option to preconfigured fabric wrapper writer
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2021-06-24 17:07:41 -06:00 |
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tangxifan
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21d1519658
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[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
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2021-06-24 16:56:28 -06:00 |
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tangxifan
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ce3c80f499
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Merge branch 'master' into dev
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2021-06-23 09:15:03 -06:00 |
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tangxifan
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cbbf601edc
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[Tool] Fix a compiler warning due to uninitialized data structure
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2021-06-18 16:20:13 -06:00 |
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tangxifan
|
fed975c52a
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[Tool] Add postfix removal support in write_io_mapping command
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2021-06-18 16:13:50 -06:00 |
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tangxifan
|
d9d57aad42
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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tangxifan
|
7ade48343c
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[Tool] Deprecate command 'write_verilog_testbench'
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2021-06-09 17:06:01 -06:00 |
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tangxifan
|
2299ce3157
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[Tool] Preconfigured testbench writer now supports icarus simulator
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2021-06-09 13:49:25 -06:00 |
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tangxifan
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3bc8e760db
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[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
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2021-06-09 11:14:45 -06:00 |
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tangxifan
|
89fb672631
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[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
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2021-06-09 10:49:00 -06:00 |
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tangxifan
|
97396eda2b
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[Tool] Add a new command 'write_simulation_task_info'
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2021-06-08 22:10:02 -06:00 |
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tangxifan
|
d2275b971d
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[Tool] Add a new command 'write_preconfigured_testbench'
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2021-06-08 21:53:51 -06:00 |
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tangxifan
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85679c0fe2
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[Tool] Bug fix in the top testbench switch due to fast configuration
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2021-06-08 21:32:26 -06:00 |
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tangxifan
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8db19c7af9
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[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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2021-06-08 21:28:16 -06:00 |
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tangxifan
|
5075c68418
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[Tool] Remove duplicated codes on fast configuration
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2021-06-08 20:58:04 -06:00 |
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tangxifan
|
4aef9d5c96
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[Tool] Remove redundant codes
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2021-06-07 21:54:01 -06:00 |
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tangxifan
|
366dcff75d
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[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
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2021-06-07 21:49:31 -06:00 |
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tangxifan
|
9808b61b36
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[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
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2021-06-07 20:06:39 -06:00 |
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tangxifan
|
ba75c18378
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[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
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2021-06-07 17:40:07 -06:00 |
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tangxifan
|
1a5902ca74
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[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
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2021-06-07 14:32:56 -06:00 |
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tangxifan
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af298de121
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[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
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2021-06-07 13:53:32 -06:00 |
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tangxifan
|
d644b8f22d
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[Tool] Support external bitstream file when generating full testbench for frame-based decoder
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2021-06-07 11:55:11 -06:00 |
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tangxifan
|
618b04568f
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[Tool] Remove unnecessary new line in bitstream file
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2021-06-04 20:07:42 -06:00 |
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tangxifan
|
cf7addb1a6
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[Tool] Add heads to bitstream plain text file
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2021-06-04 19:48:48 -06:00 |
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tangxifan
|
70fb3a85dc
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[Tool] Patch fast configuration in bitstream writing
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2021-06-04 17:23:10 -06:00 |
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tangxifan
|
d98be9f87b
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[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
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2021-06-04 16:45:00 -06:00 |
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tangxifan
|
6e69c2d70a
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[Tool] Patch fast configuration in full Verilog testbench generator
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2021-06-04 16:34:55 -06:00 |
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tangxifan
|
061f832429
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[Tool] Enable fast configuration when writing fabric bitstream
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2021-06-04 16:23:40 -06:00 |
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tangxifan
|
81048d3698
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[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
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2021-06-04 11:26:39 -06:00 |
|
tangxifan
|
98308133c1
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[Tool] Add configuration skip capability to top testbench which loads external bitstream file
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2021-06-04 11:24:05 -06:00 |
|
tangxifan
|
adb18d28b8
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[Tool] Remove unused arguments
|
2021-06-04 10:37:28 -06:00 |