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improve adder chain arch XML to support sequential output for sumout

This commit is contained in:
tangxifan 2020-04-07 15:39:37 -06:00
parent 26d1261c1f
commit 628ea3b654
8 changed files with 127 additions and 88 deletions
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27
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
View File

@ -371,21 +371,26 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

27
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
View File

@ -408,21 +408,26 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

27
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
View File

@ -371,21 +371,26 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

27
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
View File

@ -408,21 +408,26 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

27
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
View File

@ -474,21 +474,26 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

27
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
View File

@ -442,21 +442,26 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

26
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
View File

@ -411,21 +411,25 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

27
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
View File

@ -408,21 +408,26 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
<direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
<direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
<direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux>
<mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
<delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
</mux>
<mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>