adapt analysis SDC writer for routing modules
This commit is contained in:
tangxifan
parent
543cff58b9
commit
6474183539
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@ -0,0 +1,528 @@
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/********************************************************************
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* This file includes functions that are used to output a SDC file
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* that constrain routing modules of a FPGA fabric (P&Red netlist)
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* using a benchmark
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*******************************************************************/
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#include <map>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_side_manager.h"
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#include "openfpga_port.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "sdc_writer_utils.h"
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#include "analysis_sdc_writer_utils.h"
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#include "analysis_sdc_routing_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function will disable
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* 1. all the unused port (unmapped by a benchmark) of a connection block
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* 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers
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* in a connection block
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*******************************************************************/
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static
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void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const VprRoutingAnnotation& routing_annotation,
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const DeviceRRGSB& device_rr_gsb,
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const RRGSB& rr_gsb,
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const t_rr_type& cb_type,
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const bool& compact_routing_hierarchy) {
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/* Validate file stream */
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valid_file_stream(fp);
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
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std::string cb_instance_name = generate_connection_block_module_name(cb_type, gsb_coordinate);
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/* If we use the compact routing hierarchy, we need to find the module name !*/
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vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
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if (true == compact_routing_hierarchy) {
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vtr::Point<size_t> cb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
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cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type));
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cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type));
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}
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std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate);
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ModuleId cb_module = module_manager.find_module(cb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Disable timing for Connection block " << cb_module_name << std::endl;
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fp << "##################################################" << std::endl;
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/* Disable all the input port (routing tracks), which are not used by benchmark */
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for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
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const RRNodeId& chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack);
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/* Check if this node is used by benchmark */
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if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, chan_node)) {
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continue;
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}
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/* Disable both input of the routing track if it is not used! */
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std::string port_name = generate_cb_module_track_port_name(cb_type,
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itrack,
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IN_PORT);
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
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fp << "set_disable_timing ";
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fp << cb_instance_name << "/";
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fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
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fp << std::endl;
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}
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/* Disable all the output port (routing tracks), which are not used by benchmark */
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for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
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const RRNodeId& chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack);
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/* Check if this node is used by benchmark */
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if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, chan_node)) {
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continue;
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}
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/* Disable both input of the routing track if it is not used! */
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std::string port_name = generate_cb_module_track_port_name(cb_type,
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itrack,
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OUT_PORT);
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
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fp << "set_disable_timing ";
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fp << cb_instance_name << "/";
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fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
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fp << std::endl;
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}
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/* Build a map between mux_instance name and net_num */
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std::map<std::string, ClusterNetId> mux_instance_to_net_map;
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/* Disable all the output port (grid input pins), which are not used by benchmark */
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std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
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for (size_t side = 0; side < cb_sides.size(); ++side) {
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enum e_side cb_ipin_side = cb_sides[side];
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for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
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RRNodeId ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
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/* Find the MUX instance that drives the IPIN! */
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std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_graph.node_side(ipin_node), inode, std::string(""));
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mux_instance_to_net_map[mux_instance_name] = routing_annotation.rr_node_net(ipin_node);
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if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, ipin_node)) {
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continue;
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}
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if (0 == std::distance(rr_graph.node_configurable_in_edges(ipin_node).begin(), rr_graph.node_configurable_in_edges(ipin_node).end())) {
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continue;
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}
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std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
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rr_graph.node_pin_num(ipin_node));
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/* Find the port in unique mirror! */
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if (true == compact_routing_hierarchy) {
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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vtr::Point<size_t> cb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
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const RRNodeId& unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode);
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port_name = generate_cb_module_grid_port_name(cb_ipin_side,
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rr_graph.node_pin_num(unique_mirror_ipin_node));
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}
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
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fp << "set_disable_timing ";
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fp << cb_instance_name << "/";
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fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
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fp << std::endl;
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}
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}
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/* Disable all the unused inputs of routing multiplexers, which are not used by benchmark
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* Here, we start from each input of the Connection Blocks, and traverse forward to the sink
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* port of the module net whose source is the input
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* We will find the instance name which is the parent of the sink port, and search the
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* net id through the instance_name_to_net_map
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* The the net id does not match the net id of this input, we will disable the sink port!
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*
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* cb_module
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* +-----------------------
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* | MUX instance A
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* | +-----------
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* input_port--->|--+---x-->| sink port (disable!)
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* | | +----------
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* | | MUX instance B
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* | | +----------
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* | +------>| sink port (do not disable!)
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*/
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for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
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const RRNodeId& chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack);
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/* Disable both input of the routing track if it is not used! */
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std::string port_name = generate_cb_module_track_port_name(cb_type,
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itrack,
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OUT_PORT);
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
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disable_analysis_module_input_port_net_sinks(fp,
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module_manager, cb_module,
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cb_instance_name,
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module_port,
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routing_annotation,
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chan_node,
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mux_instance_to_net_map);
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}
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}
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/********************************************************************
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* Iterate over all the connection blocks in a device
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* and disable unused ports for each of them
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*******************************************************************/
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static
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void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const VprRoutingAnnotation& routing_annotation,
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const DeviceRRGSB& device_rr_gsb,
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const t_rr_type& cb_type,
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const bool& compact_routing_hierarchy) {
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/* Build unique X-direction connection block modules */
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vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
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for (size_t ix = 0; ix < cb_range.x(); ++ix) {
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for (size_t iy = 0; iy < cb_range.y(); ++iy) {
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/* Check if the connection block exists in the device!
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* Some of them do NOT exist due to heterogeneous blocks (height > 1)
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* We will skip those modules
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*/
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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if (false == rr_gsb.is_cb_exist(cb_type)) {
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continue;
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}
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print_analysis_sdc_disable_cb_unused_resources(fp,
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module_manager,
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rr_graph,
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routing_annotation,
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device_rr_gsb,
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rr_gsb,
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cb_type,
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compact_routing_hierarchy);
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}
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}
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}
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/********************************************************************
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* Iterate over all the connection blocks in a device
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* and disable unused ports for each of them
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*******************************************************************/
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void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const VprRoutingAnnotation& routing_annotation,
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const DeviceRRGSB& device_rr_gsb,
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const bool& compact_routing_hierarchy) {
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print_analysis_sdc_disable_unused_cb_ports(fp, module_manager,
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rr_graph,
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routing_annotation,
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device_rr_gsb,
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CHANX, compact_routing_hierarchy);
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print_analysis_sdc_disable_unused_cb_ports(fp, module_manager,
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rr_graph,
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routing_annotation,
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device_rr_gsb,
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CHANY, compact_routing_hierarchy);
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}
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/********************************************************************
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* This function will disable
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* 1. all the unused port (unmapped by a benchmark) of a switch block
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* 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers
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* in a switch block
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*******************************************************************/
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static
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void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const VprRoutingAnnotation& routing_annotation,
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const DeviceRRGSB& device_rr_gsb,
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const RRGSB& rr_gsb,
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const bool& compact_routing_hierarchy) {
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/* Validate file stream */
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valid_file_stream(fp);
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate);
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/* If we use the compact routing hierarchy, we need to find the module name !*/
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vtr::Point<size_t> sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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if (true == compact_routing_hierarchy) {
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vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
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sb_coordinate.set_x(unique_mirror.get_sb_x());
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sb_coordinate.set_y(unique_mirror.get_sb_y());
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}
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std::string sb_module_name = generate_switch_block_module_name(sb_coordinate);
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ModuleId sb_module = module_manager.find_module(sb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Disable timing for Switch block " << sb_module_name << std::endl;
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fp << "##################################################" << std::endl;
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/* Build a map between mux_instance name and net_num */
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std::map<std::string, ClusterNetId> mux_instance_to_net_map;
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/* Disable all the input/output port (routing tracks), which are not used by benchmark */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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SideManager side_manager(side);
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for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
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const RRNodeId& chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
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std::string port_name = generate_sb_module_track_port_name(rr_graph.node_type(rr_gsb.get_chan_node(side_manager.get_side(), itrack)),
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side_manager.get_side(), itrack,
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rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
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if (true == compact_routing_hierarchy) {
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
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port_name = generate_sb_module_track_port_name(rr_graph.node_type(unique_mirror.get_chan_node(side_manager.get_side(), itrack)),
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side_manager.get_side(), itrack,
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unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack));
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}
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
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/* Cache the net name for routing tracks which are outputs of the switch block */
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if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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/* Generate the name of mux instance related to this output node */
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std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, side_manager.get_side(), itrack, std::string(""));
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mux_instance_to_net_map[mux_instance_name] = routing_annotation.rr_node_net(chan_node);
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}
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/* Check if this node is used by benchmark */
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if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, chan_node)) {
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continue;
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}
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fp << "set_disable_timing ";
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fp << sb_instance_name << "/";
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fp << generate_sdc_port(module_manager.module_port(sb_module, module_port));
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fp << std::endl;
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}
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}
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/* Disable all the input port (grid output pins), which are not used by benchmark */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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SideManager side_manager(side);
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for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
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const RRNodeId& opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode);
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std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
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rr_graph.node_side(opin_node),
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rr_graph.node_pin_num(opin_node));
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if (true == compact_routing_hierarchy) {
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
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const RRNodeId& unique_mirror_opin_node = unique_mirror.get_opin_node(side_manager.get_side(), inode);
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port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
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rr_graph.node_side(unique_mirror_opin_node),
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rr_graph.node_pin_num(unique_mirror_opin_node));
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}
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
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/* Check if this node is used by benchmark */
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if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, opin_node)) {
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continue;
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}
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fp << "set_disable_timing ";
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fp << sb_instance_name << "/";
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fp << generate_sdc_port(module_manager.module_port(sb_module, module_port));
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fp << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable all the unused inputs of routing multiplexers, which are not used by benchmark
|
||||
* Here, we start from each input of the Switch Blocks, and traverse forward to the sink
|
||||
* port of the module net whose source is the input
|
||||
* We will find the instance name which is the parent of the sink port, and search the
|
||||
* net id through the instance_name_to_net_map
|
||||
* The the net id does not match the net id of this input, we will disable the sink port!
|
||||
*
|
||||
* sb_module
|
||||
* +-----------------------
|
||||
* | MUX instance A
|
||||
* | +-----------
|
||||
* input_port--->|--+---x-->| sink port (disable! net_id = Y)
|
||||
* (net_id = X) | | +----------
|
||||
* | | MUX instance B
|
||||
* | | +----------
|
||||
* | +------>| sink port (do not disable! net_id = X)
|
||||
*
|
||||
* Because the input ports of a SB module come from
|
||||
* 1. Grid output pins
|
||||
* 2. routing tracks
|
||||
* We will walk through these ports and do conditionally disable_timing
|
||||
*/
|
||||
|
||||
/* Iterate over input ports coming from grid output pins */
|
||||
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
|
||||
SideManager side_manager(side);
|
||||
|
||||
for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
|
||||
const RRNodeId& opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode);
|
||||
|
||||
std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
|
||||
rr_graph.node_side(opin_node),
|
||||
rr_graph.node_pin_num(opin_node));
|
||||
|
||||
if (true == compact_routing_hierarchy) {
|
||||
/* Note: use GSB coordinate when inquire for unique modules!!! */
|
||||
vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
|
||||
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
|
||||
const RRNodeId& unique_mirror_opin_node = unique_mirror.get_opin_node(side_manager.get_side(), inode);
|
||||
|
||||
port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
|
||||
rr_graph.node_side(unique_mirror_opin_node),
|
||||
rr_graph.node_pin_num(unique_mirror_opin_node));
|
||||
}
|
||||
|
||||
|
||||
/* Ensure we have this port in the module! */
|
||||
ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
|
||||
VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
|
||||
|
||||
disable_analysis_module_input_port_net_sinks(fp, module_manager,
|
||||
sb_module,
|
||||
sb_instance_name,
|
||||
module_port,
|
||||
routing_annotation,
|
||||
opin_node,
|
||||
mux_instance_to_net_map);
|
||||
}
|
||||
}
|
||||
|
||||
/* Iterate over input ports coming from routing tracks */
|
||||
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
|
||||
SideManager side_manager(side);
|
||||
|
||||
for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
|
||||
/* Skip output ports, they have already been disabled or not */
|
||||
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
const RRNodeId& chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
|
||||
|
||||
std::string port_name = generate_sb_module_track_port_name(rr_graph.node_type(chan_node),
|
||||
side_manager.get_side(), itrack,
|
||||
rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
|
||||
|
||||
if (true == compact_routing_hierarchy) {
|
||||
/* Note: use GSB coordinate when inquire for unique modules!!! */
|
||||
vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
|
||||
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
|
||||
const RRNodeId& unique_mirror_chan_node = unique_mirror.get_chan_node(side_manager.get_side(), itrack);
|
||||
|
||||
port_name = generate_sb_module_track_port_name(rr_graph.node_type(unique_mirror_chan_node),
|
||||
side_manager.get_side(), itrack,
|
||||
unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack));
|
||||
}
|
||||
|
||||
|
||||
/* Ensure we have this port in the module! */
|
||||
ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
|
||||
VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
|
||||
|
||||
disable_analysis_module_input_port_net_sinks(fp, module_manager,
|
||||
sb_module,
|
||||
sb_instance_name,
|
||||
module_port,
|
||||
routing_annotation,
|
||||
chan_node,
|
||||
mux_instance_to_net_map);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* Iterate over all the connection blocks in a device
|
||||
* and disable unused ports for each of them
|
||||
*******************************************************************/
|
||||
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
|
||||
const ModuleManager& module_manager,
|
||||
const RRGraph& rr_graph,
|
||||
const VprRoutingAnnotation& routing_annotation,
|
||||
const DeviceRRGSB& device_rr_gsb,
|
||||
const bool& compact_routing_hierarchy) {
|
||||
|
||||
/* Build unique X-direction connection block modules */
|
||||
vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
|
||||
|
||||
for (size_t ix = 0; ix < sb_range.x(); ++ix) {
|
||||
for (size_t iy = 0; iy < sb_range.y(); ++iy) {
|
||||
/* Check if the connection block exists in the device!
|
||||
* Some of them do NOT exist due to heterogeneous blocks (height > 1)
|
||||
* We will skip those modules
|
||||
*/
|
||||
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
|
||||
if (false == rr_gsb.is_sb_exist()) {
|
||||
continue;
|
||||
}
|
||||
|
||||
print_analysis_sdc_disable_sb_unused_resources(fp,
|
||||
module_manager,
|
||||
rr_graph,
|
||||
routing_annotation,
|
||||
device_rr_gsb,
|
||||
rr_gsb,
|
||||
compact_routing_hierarchy);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
#ifndef ANALYSIS_SDC_ROUTING_WRITER_H
|
||||
#define ANALYSIS_SDC_ROUTING_WRITER_H
|
||||
|
||||
/********************************************************************
|
||||
* Include header files that are required by function declaration
|
||||
*******************************************************************/
|
||||
#include <fstream>
|
||||
#include <vector>
|
||||
#include "module_manager.h"
|
||||
#include "device_rr_gsb.h"
|
||||
|
||||
/********************************************************************
|
||||
* Function declaration
|
||||
*******************************************************************/
|
||||
|
||||
/* begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
|
||||
const ModuleManager& module_manager,
|
||||
const RRGraph& rr_graph,
|
||||
const VprRoutingAnnotation& routing_annotation,
|
||||
const DeviceRRGSB& device_rr_gsb,
|
||||
const bool& compact_routing_hierarchy);
|
||||
|
||||
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
|
||||
const ModuleManager& module_manager,
|
||||
const RRGraph& rr_graph,
|
||||
const VprRoutingAnnotation& routing_annotation,
|
||||
const DeviceRRGSB& device_rr_gsb,
|
||||
const bool& compact_routing_hierarchy);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue