start porting analysis SDC writer
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tangxifan
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a17c14c363
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543cff58b9
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/********************************************************************
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* This file includes most utilized functions
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* that are used to output a SDC file
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* in order to constrain a FPGA fabric (P&Red netlist) mapped to a benchmark
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "sdc_writer_utils.h"
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#include "analysis_sdc_writer_utils.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Identify if a node should be disabled during analysis SDC generation
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*******************************************************************/
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bool is_rr_node_to_be_disable_for_analysis(const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& cur_rr_node) {
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/* Conditions to enable timing analysis for a node
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* 1st condition: it have a valid net_number
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* TODO: 2nd condition: it is not an parasitic net
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*/
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return ClusterNetId::INVALID() == routing_annotation.rr_node_net(cur_rr_node);
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}
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/********************************************************************
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* Disable all the unused inputs of routing multiplexers, which are not used by benchmark
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* Here, we start from each input of a routing module, and traverse forward to the sink
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* port of the module net whose source is the input
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* We will find the instance name which is the parent of the sink port, and search the
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* net id through the instance_name_to_net_map
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* The the net id does not match the net id of this input, we will disable the sink port!
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*
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* parent_module
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* +-----------------------
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* | MUX instance A
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* | +-----------
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* input_port--->|--+---x-->| sink port (disable! net_id = Y)
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* (net_id = X) | | +----------
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* | | MUX instance B
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* | | +----------
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* | +------>| sink port (do not disable! net_id = X)
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*
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*******************************************************************/
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void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_instance_name,
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const ModulePortId& module_input_port,
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const size_t& module_input_pin,
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const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& input_rr_node,
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const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
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/* Validate file stream */
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valid_file_stream(fp);
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/* Find the module net which sources from this port! */
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ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, module_input_pin);
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VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net));
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/* Touch each sink of the net! */
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for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id];
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size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id];
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/* Skip when sink module is the parent module,
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* the output ports of parent modules have been disabled/enabled already!
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*/
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if (sink_module == parent_module) {
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continue;
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}
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std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance);
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bool disable_timing = false;
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/* Check if this node is used by benchmark */
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if (true == is_rr_node_to_be_disable_for_analysis(routing_annotation, input_rr_node)) {
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/* Disable all the sinks! */
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disable_timing = true;
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} else {
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std::map<std::string, ClusterNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
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if (it != mux_instance_to_net_map.end()) {
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/* See if the net id matches. If does not match, we should disable! */
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if (routing_annotation.rr_node_net(input_rr_node) != mux_instance_to_net_map.at(sink_instance_name)) {
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disable_timing = true;
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}
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}
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}
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/* Time to write SDC command to disable timing or not */
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if (false == disable_timing) {
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continue;
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}
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BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
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sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
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module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
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/* Get the input id that is used! Disable the unused inputs! */
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fp << "set_disable_timing ";
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fp << parent_instance_name << "/";
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fp << sink_instance_name << "/";
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fp << generate_sdc_port(sink_port);
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fp << std::endl;
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}
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}
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/********************************************************************
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* Disable all the unused inputs of routing multiplexers, which are not used by benchmark
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* Here, we start from each input of a routing module, and traverse forward to the sink
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* port of the module net whose source is the input
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* We will find the instance name which is the parent of the sink port, and search the
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* net id through the instance_name_to_net_map
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* The the net id does not match the net id of this input, we will disable the sink port!
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*
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* parent_module
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* +-----------------------
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* | MUX instance A
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* | +-----------
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* input_port--->|--+---x-->| sink port (disable! net_id = Y)
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* (net_id = X) | | +----------
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* | | MUX instance B
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* | | +----------
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* | +------>| sink port (do not disable! net_id = X)
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*
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*******************************************************************/
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void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_instance_name,
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const ModulePortId& module_input_port,
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const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& input_rr_node,
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const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
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/* Validate file stream */
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valid_file_stream(fp);
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/* Find the module net which sources from this port! */
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for (const size_t& pin : module_manager.module_port(parent_module, module_input_port).pins()) {
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disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module,
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parent_instance_name,
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module_input_port, pin,
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routing_annotation, input_rr_node,
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mux_instance_to_net_map);
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}
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}
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/********************************************************************
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* Disable all the unused inputs of routing multiplexers, which are not used by benchmark
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* Here, we start from each output of a child module, and traverse forward to the sink
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* port of the module net whose source is the input
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* We will find the instance name which is the parent of the sink port, and search the
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* net id through the instance_name_to_net_map
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* The the net id does not match the net id of this input, we will disable the sink port!
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*
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* Parent_module
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* +---------------------------------------------
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* |
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* | +--------------------------------------------+
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* | | MUX child_module |
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* | | +-------------+ +-----------+ |
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* | +--->| Routing |------>| | |
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* input_pin0(netA) --->|----x--->| Multiplexer | netA | output_pin|-----+
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* | +-------------+ | | netA
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* | | |
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*
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*
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*******************************************************************/
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void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_instance_name,
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const ModuleId& child_module,
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const size_t& child_instance,
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const ModulePortId& child_module_port,
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const size_t& child_module_pin,
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const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& output_rr_node,
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const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
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/* Validate file stream */
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valid_file_stream(fp);
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/* Find the module net which sources from this port! */
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ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, child_module, child_instance, child_module_port, child_module_pin);
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VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net));
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/* Touch each sink of the net! */
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for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id];
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size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id];
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/* Skip when sink module is the parent module,
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* the output ports of parent modules have been disabled/enabled already!
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*/
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if (sink_module == parent_module) {
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continue;
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}
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std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance);
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bool disable_timing = false;
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/* Check if this node is used by benchmark */
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if (true == is_rr_node_to_be_disable_for_analysis(routing_annotation, output_rr_node)) {
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/* Disable all the sinks! */
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disable_timing = true;
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} else {
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std::map<std::string, ClusterNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
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if (it != mux_instance_to_net_map.end()) {
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/* See if the net id matches. If does not match, we should disable! */
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if (routing_annotation.rr_node_net(output_rr_node) != mux_instance_to_net_map.at(sink_instance_name)) {
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disable_timing = true;
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}
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}
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}
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/* Time to write SDC command to disable timing or not */
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if (false == disable_timing) {
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continue;
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}
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BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
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sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
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module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
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/* Get the input id that is used! Disable the unused inputs! */
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fp << "set_disable_timing ";
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fp << parent_instance_name << "/";
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fp << sink_instance_name << "/";
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fp << generate_sdc_port(sink_port);
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fp << std::endl;
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}
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}
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} /* end namespace openfpga */
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@ -0,0 +1,57 @@
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#ifndef ANALYSIS_SDC_WRITER_UTILS_H
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#define ANALYSIS_SDC_WRITER_UTILS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <fstream>
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#include <string>
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#include <map>
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#include "module_manager.h"
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#include "rr_graph_obj.h"
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#include "vpr_routing_annotation.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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bool is_rr_node_to_be_disable_for_analysis(const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& cur_rr_node);
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void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_instance_name,
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const ModulePortId& module_input_port,
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const size_t& module_input_pin,
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const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& input_rr_node,
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const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
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void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_instance_name,
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const ModulePortId& module_input_port,
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const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& input_rr_node,
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const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
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void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_instance_name,
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const ModuleId& child_module,
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const size_t& child_instance,
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const ModulePortId& child_module_port,
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const size_t& child_module_pin,
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const VprRoutingAnnotation& routing_annotation,
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const RRNodeId& output_rr_node,
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const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
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} /* end namespace openfpga */
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#endif
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