adapt pnr sdc grid writer
This commit is contained in:
tangxifan
parent
b4ed931ac6
commit
fdcb982903
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@ -1103,7 +1103,6 @@ void build_grid_modules(ModuleManager& module_manager,
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duplicate_grid_pin,
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verbose);
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}
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continue;
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} else {
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/* For CLB and heterogenenous blocks */
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build_physical_tile_module(module_manager, circuit_lib,
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@ -0,0 +1,346 @@
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/********************************************************************
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* This file includes functions that print SDC (Synopsys Design Constraint)
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* files in physical design tools, i.e., Place & Route (PnR) tools
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* The SDC files are used to constrain the physical design for each grid
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* (CLBs, heterogeneous blocks etc.)
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*
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* Note that this is different from the SDC to constrain VPR Place&Route
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* engine! These SDCs are designed for PnR to generate FPGA layouts!!!
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*******************************************************************/
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#include <ctime>
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#include <fstream>
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "openfpga_side_manager.h"
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#include "openfpga_interconnect_types.h"
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#include "vpr_utils.h"
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#include "mux_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "pb_type_utils.h"
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#include "pb_graph_utils.h"
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#include "sdc_writer_naming.h"
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#include "sdc_writer_utils.h"
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#include "pnr_sdc_grid_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print pin-to-pin timing constraints for a given interconnection
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* at an output port of a pb_graph node
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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t_pb_graph_pin* des_pb_graph_pin,
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t_mode* physical_mode) {
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/* Validate file stream */
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valid_file_stream(fp);
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/* 1. identify pin interconnection type,
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* 2. Identify the number of fan-in (Consider interconnection edges of only selected mode)
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* 3. Print SDC timing constraints
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*/
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t_interconnect* cur_interc = pb_graph_pin_interc(des_pb_graph_pin, physical_mode);
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size_t fan_in = pb_graph_pin_inputs(des_pb_graph_pin, cur_interc).size();
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if ((nullptr == cur_interc) || (0 == fan_in)) {
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/* No interconnection matched */
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return;
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}
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/* Print pin-to-pin SDC contraint here */
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/* For more than one mode defined, the direct interc has more than one input_edge ,
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* We need to find which edge is connected the pin we want
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*/
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for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) {
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if (cur_interc != des_pb_graph_pin->input_edges[iedge]->interconnect) {
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continue;
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}
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/* Source pin, node, pb_type*/
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t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0];
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t_pb_graph_node* src_pb_graph_node = src_pb_graph_pin->parent_node;
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/* Des pin, node, pb_type */
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t_pb_graph_node* des_pb_graph_node = des_pb_graph_pin->parent_node;
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/* Find the src module in module manager */
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std::string src_module_name = generate_physical_block_module_name(src_pb_graph_pin->parent_node->pb_type);
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ModuleId src_module = module_manager.find_module(src_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(src_module));
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ModulePortId src_module_port_id = module_manager.find_module_port(src_module, generate_pb_type_port_name(src_pb_graph_pin->port));
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VTR_ASSERT(true == module_manager.valid_module_port_id(src_module, src_module_port_id));
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/* Generate the name of the des instance name
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* If des module is not the parent module, it is a child module.
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* We should find the instance id
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*/
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std::string src_instance_name = src_module_name;
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if (parent_module != src_module) {
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src_instance_name = module_manager.module_name(parent_module) + std::string("/");
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/* Instance id is actually the placement index */
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size_t instance_id = src_pb_graph_node->placement_index;
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if (true == module_manager.instance_name(parent_module, src_module, instance_id).empty()) {
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src_instance_name += src_module_name;
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src_instance_name += "_";
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src_instance_name += std::to_string(instance_id);
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src_instance_name += "_";
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} else {
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src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id);
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}
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}
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/* Generate src port information */
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BasicPort src_port = module_manager.module_port(src_module, src_module_port_id);
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src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number);
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/* Find the des module in module manager */
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std::string des_module_name = generate_physical_block_module_name(des_pb_graph_pin->parent_node->pb_type);
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ModuleId des_module = module_manager.find_module(des_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(des_module));
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ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port));
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VTR_ASSERT(true == module_manager.valid_module_port_id(des_module, des_module_port_id));
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/* Generate the name of the des instance name
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* If des module is not the parent module, it is a child module.
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* We should find the instance id
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*/
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std::string des_instance_name = des_module_name;
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if (parent_module != des_module) {
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des_instance_name = module_manager.module_name(parent_module) + std::string("/");
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/* Instance id is actually the placement index */
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size_t instance_id = des_pb_graph_node->placement_index;
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if (true == module_manager.instance_name(parent_module, des_module, instance_id).empty()) {
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des_instance_name += des_module_name;
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des_instance_name += "_";
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des_instance_name += std::to_string(instance_id);
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des_instance_name += "_";
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} else {
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des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id);
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}
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}
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/* Generate des port information */
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BasicPort des_port = module_manager.module_port(des_module, des_module_port_id);
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des_port.set_width(des_pb_graph_pin->pin_number, des_pb_graph_pin->pin_number);
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/* Print a SDC timing constraint */
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print_pnr_sdc_constrain_max_delay(fp,
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src_instance_name,
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generate_sdc_port(src_port),
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des_instance_name,
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generate_sdc_port(des_port),
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des_pb_graph_pin->input_edges[iedge]->delay_max);
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}
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}
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/********************************************************************
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* Print port-to-port timing constraints which source from
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* an output port of a pb_graph node
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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t_pb_graph_node* des_pb_graph_node,
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const e_circuit_pb_port_type& pb_port_type,
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t_mode* physical_mode) {
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/* Validate file stream */
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valid_file_stream(fp);
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switch (pb_port_type) {
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case CIRCUIT_PB_PORT_INPUT: {
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for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) {
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/* If this is a idle block, we set 0 to the selected edge*/
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/* Get the selected edge of current pin*/
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print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
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module_manager, parent_module,
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&(des_pb_graph_node->input_pins[iport][ipin]),
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physical_mode);
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}
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}
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break;
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}
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case CIRCUIT_PB_PORT_OUTPUT: {
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for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) {
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print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
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module_manager, parent_module,
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&(des_pb_graph_node->output_pins[iport][ipin]),
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physical_mode);
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}
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}
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break;
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}
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case CIRCUIT_PB_PORT_CLOCK: {
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/* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */
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break;
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}
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid pb port type!\n");
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exit(1);
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}
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}
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/********************************************************************
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* This function will generate a SDC file for each pb_type,
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* constraining the pin-to-pin timing between
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* 1. input port of parent_pb_graph_node and input port of child_pb_graph_nodes
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* 2. output port of parent_pb_graph_node and output port of child_pb_graph_nodes
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* 3. output port of child_pb_graph_node and input port of child_pb_graph_nodes
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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t_pb_graph_node* parent_pb_graph_node,
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t_mode* physical_mode) {
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/* Get the pb_type definition related to the node */
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t_pb_type* physical_pb_type = parent_pb_graph_node->pb_type;
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std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
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/* Find the pb module in module manager */
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ModuleId pb_module = module_manager.find_module(pb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
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/* Create the file name for SDC */
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std::string sdc_fname(sdc_dir + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX));
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(sdc_fname.c_str(), fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR"));
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/* We check output_pins of cur_pb_graph_node and its the input_edges
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* Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node
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* child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins
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* /|\
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* |
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* input_pins, edges, output_pins
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*/
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print_pnr_sdc_constrain_pb_interc_timing(fp,
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module_manager, pb_module,
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parent_pb_graph_node,
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CIRCUIT_PB_PORT_OUTPUT,
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physical_mode);
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/* We check input_pins of child_pb_graph_node and its the input_edges
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* Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node
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* cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins
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* /|\
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* |
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* input_pins, edges, output_pins
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*/
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for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
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for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
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t_pb_graph_node* child_pb_graph_node = &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]);
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/* For each child_pb_graph_node input pins*/
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print_pnr_sdc_constrain_pb_interc_timing(fp,
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module_manager, pb_module,
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child_pb_graph_node,
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CIRCUIT_PB_PORT_INPUT,
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physical_mode);
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/* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */
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}
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}
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Recursively print SDC timing constraints for a pb_type
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* This function will generate a SDC file for each pb_type,
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* constraining the pin-to-pin timing
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*******************************************************************/
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static
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void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const VprDeviceAnnotation& device_annotation,
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t_pb_graph_node* parent_pb_graph_node) {
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/* Validate pb_graph node */
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if (nullptr == parent_pb_graph_node) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid parent_pb_graph_node.\n");
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exit(1);
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}
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/* Get the pb_type */
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t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type;
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/* No need to constrain the primitive node */
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if (true == is_primitive_pb_type(parent_pb_type)) {
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return;
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}
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/* Note we only go through the graph through the physical modes.
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* which we build the modules
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*/
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t_mode* physical_mode = device_annotation.physical_mode(parent_pb_type);
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/* Write a SDC file for this pb_type */
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print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir,
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module_manager,
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parent_pb_graph_node,
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physical_mode);
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/* Go recursively to the lower level in the pb_graph
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* Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type
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*/
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for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
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rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager,
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device_annotation,
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&(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
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}
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}
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/********************************************************************
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* Top-level function to print timing constraints for pb_types
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*******************************************************************/
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void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
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const DeviceContext& device_ctx,
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const VprDeviceAnnotation& device_annotation,
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const ModuleManager& module_manager) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Generating SDC for constraining grid timing for P&R flow");
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for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
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/* Bypass empty type or nullptr */
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if (true == is_empty_type(&physical_tile)) {
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continue;
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} else {
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VTR_ASSERT(1 == physical_tile.equivalent_sites.size());
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t_pb_graph_node* pb_graph_head = physical_tile.equivalent_sites[0]->pb_graph_head;
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if (nullptr == pb_graph_head) {
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continue;
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}
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/* Special for I/O block, generate one module for each border side */
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rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager,
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device_annotation,
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pb_graph_head);
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}
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}
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}
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} /* end namespace openfpga */
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@ -0,0 +1,27 @@
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#ifndef PNR_SDC_GRID_WRITER_H
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#define PNR_SDC_GRID_WRITER_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include <vector>
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#include "vpr_context.h"
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#include "vpr_device_annotation.h"
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#include "module_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
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const DeviceContext& device_ctx,
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const VprDeviceAnnotation& device_annotation,
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const ModuleManager& module_manager);
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} /* end namespace openfpga */
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#endif
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