bring pnr sdc generator online and fixed minor bugs in bitstream writing
This commit is contained in:
tangxifan
parent
e45fa18c4c
commit
092e10afda
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@ -5,6 +5,9 @@
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#include "vtr_time.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "build_device_bitstream.h"
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#include "bitstream_writer.h"
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#include "build_fabric_bitstream.h"
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@ -30,6 +33,11 @@ void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
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cmd_context.option_enable(cmd, opt_verbose));
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if (true == cmd_context.option_enable(cmd, opt_file)) {
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std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
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/* Create directories */
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create_dir_path(src_dir_path.c_str());
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write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(),
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cmd_context.option_value(cmd, opt_file));
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}
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@ -0,0 +1,80 @@
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/********************************************************************
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* This file includes functions to compress the hierachy of routing architecture
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "circuit_library_utils.h"
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#include "pnr_sdc_writer.h"
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#include "openfpga_sdc.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A wrapper function to call the PnR SDC generator of FPGA-SDC
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*******************************************************************/
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void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
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CommandOptionId opt_constrain_grid = cmd.option("constrain_grid");
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CommandOptionId opt_constrain_sb = cmd.option("constrain_sb");
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CommandOptionId opt_constrain_cb = cmd.option("constrain_cb");
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CommandOptionId opt_constrain_configurable_memory_outputs = cmd.option("constrain_configurable_memory_outputs");
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CommandOptionId opt_constrain_routing_multiplexer_outputs = cmd.option("constrain_routing_multiplexer_outputs");
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CommandOptionId opt_constrain_switch_block_outputs = cmd.option("constrain_switch_block_outputs");
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/* This is an intermediate data structure which is designed to modularize the FPGA-SDC
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* Keep it independent from any other outside data structures
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*/
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std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
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/* Create directories */
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create_dir_path(sdc_dir_path.c_str());
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PnrSdcOption options(sdc_dir_path);
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options.set_constrain_global_port(cmd_context.option_enable(cmd, opt_constrain_global_port));
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options.set_constrain_grid(cmd_context.option_enable(cmd, opt_constrain_grid));
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options.set_constrain_sb(cmd_context.option_enable(cmd, opt_constrain_sb));
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options.set_constrain_cb(cmd_context.option_enable(cmd, opt_constrain_cb));
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options.set_constrain_configurable_memory_outputs(cmd_context.option_enable(cmd, opt_constrain_configurable_memory_outputs));
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options.set_constrain_routing_multiplexer_outputs(cmd_context.option_enable(cmd, opt_constrain_routing_multiplexer_outputs));
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options.set_constrain_switch_block_outputs(cmd_context.option_enable(cmd, opt_constrain_switch_block_outputs));
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/* We first turn on default sdc option and then disable part of them by following users' options */
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if (false == options.generate_sdc_pnr()) {
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options.set_generate_sdc_pnr(true);
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}
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/* Collect global ports from the circuit library:
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* TODO: should we place this in the OpenFPGA context?
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*/
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std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(openfpga_ctx.arch().circuit_lib);
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/* Execute only when sdc is enabled */
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if (true == options.generate_sdc_pnr()) {
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print_pnr_sdc(options,
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0, /* TODO: add critical path stats to OpenFPGA context */
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//openfpga_ctx.vpr_timing_annotation().critical_path_delay();
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g_vpr_ctx.device(),
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.device_rr_gsb(),
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openfpga_ctx.module_graph(),
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openfpga_ctx.mux_lib(),
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openfpga_ctx.arch().circuit_lib,
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global_ports,
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openfpga_ctx.flow_manager().compress_routing());
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}
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}
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} /* end namespace openfpga */
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@ -0,0 +1,23 @@
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#ifndef OPENFPGA_SDC_H
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#define OPENFPGA_SDC_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "command.h"
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#include "command_context.h"
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#include "openfpga_context.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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} /* end namespace openfpga */
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#endif
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@ -0,0 +1,79 @@
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/********************************************************************
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* Add commands to the OpenFPGA shell interface,
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* in purpose of generate SDC files
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* - write_pnr_sdc : generate SDC to constrain the back-end flow for FPGA fabric
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* - write_analysis_sdc: TODO: generate SDC based on users' implementations
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*******************************************************************/
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#include "openfpga_sdc.h"
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#include "openfpga_sdc_command.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* - Add a command to Shell environment: generate PnR SDC
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static
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void add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const ShellCommandId& shell_cmd_build_fabric_id) {
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Command shell_cmd("write_pnr_sdc");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for SDC files");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--constrain_global_port' */
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shell_cmd.add_option("constrain_global_port", false, "Constrain all the global ports of FPGA fabric");
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/* Add an option '--constrain_grid' */
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shell_cmd.add_option("constrain_grid", false, "Constrain all the grids of FPGA fabric");
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/* Add an option '--constrain_sb' */
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shell_cmd.add_option("constrain_sb", false, "Constrain all the switch blocks of FPGA fabric");
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/* Add an option '--constrain_cb' */
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shell_cmd.add_option("constrain_cb", false, "Constrain all the connection blocks of FPGA fabric");
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/* Add an option '--constrain_configurable_memory_outputs' */
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shell_cmd.add_option("constrain_configurable_memory_outputs", false, "Constrain all the outputs of configurable memories of FPGA fabric");
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/* Add an option '--constrain_routing_multiplexer_outputs' */
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shell_cmd.add_option("constrain_routing_multiplexer_outputs", false, "Constrain all the outputs of routing multiplexer of FPGA fabric");
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/* Add an option '--constrain_switch_block_outputs' */
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shell_cmd.add_option("constrain_switch_block_outputs", false, "Constrain all the outputs of switch blocks of FPGA fabric");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to constrain the backend flow for FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_pnr_sdc);
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/* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
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std::vector<ShellCommandId> cmd_dependency;
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cmd_dependency.push_back(shell_cmd_build_fabric_id);
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shell.set_command_dependency(shell_cmd_id, cmd_dependency);
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}
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void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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/* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
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const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_sdc_cmd_class = shell.add_command_class("FPGA-SDC");
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/********************************
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* Command 'write_fabric_verilog'
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*/
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add_openfpga_write_pnr_sdc_command(shell,
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openfpga_sdc_cmd_class,
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shell_cmd_build_fabric_id);
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}
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} /* end namespace openfpga */
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@ -0,0 +1,21 @@
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#ifndef OPENFPGA_SDC_COMMAND_H
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#define OPENFPGA_SDC_COMMAND_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "shell.h"
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#include "openfpga_context.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell);
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} /* end namespace openfpga */
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#endif
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@ -323,7 +323,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Generating SDC for constraining grid timing for P&R flow");
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vtr::ScopedStartFinishTimer timer("Write SDC for constraining grid timing for P&R flow");
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for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
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/* Bypass empty type or nullptr */
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@ -166,7 +166,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
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const DeviceRRGSB& device_rr_gsb) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Switch Block timing for P&R flow");
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
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/* Get the range of SB array */
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vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
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@ -195,7 +195,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
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const DeviceRRGSB& device_rr_gsb) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Switch Block timing for P&R flow");
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
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for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
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const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
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@ -362,7 +362,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
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const DeviceRRGSB& device_rr_gsb) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Connection Block timing for P&R flow");
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
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print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager,
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rr_graph,
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@ -385,7 +385,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
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const DeviceRRGSB& device_rr_gsb) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Connection Block timing for P&R flow");
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
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/* Print SDC for unique X-direction connection block modules */
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for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
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@ -58,7 +58,7 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
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std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
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std::string timer_message = std::string("Write SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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@ -153,7 +153,7 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable configurable memory outputs for P&R flow '") + sdc_fname + std::string("'");
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std::string timer_message = std::string("Write SDC to disable configurable memory outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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@ -187,7 +187,7 @@ void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
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std::string timer_message = std::string("Write SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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@ -242,7 +242,7 @@ void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::strin
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
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std::string timer_message = std::string("Write SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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@ -298,7 +298,7 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
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std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
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/* Start time count */
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std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
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std::string timer_message = std::string("Write SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Create the file stream */
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@ -14,6 +14,7 @@
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#include "openfpga_setup_command.h"
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#include "openfpga_verilog_command.h"
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#include "openfpga_bitstream_command.h"
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#include "openfpga_sdc_command.h"
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#include "basic_command.h"
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#include "openfpga_title.h"
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@ -60,6 +61,9 @@ int main(int argc, char** argv) {
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/* Add openfpga bitstream commands */
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openfpga::add_openfpga_bitstream_commands(shell);
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/* Add openfpga sdc commands */
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openfpga::add_openfpga_sdc_commands(shell);
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/* Add basic commands: exit, help, etc.
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* Note:
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* This MUST be the last command group to be added!
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@ -35,10 +35,19 @@ fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepene
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
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write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC
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# Finish and exit OpenFPGA
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exit
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