use constant openfpga context in SDC generator
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@ -28,7 +28,7 @@ namespace openfpga {
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/********************************************************************
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* A wrapper function to call the PnR SDC generator of FPGA-SDC
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*******************************************************************/
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int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
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int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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@ -168,7 +168,7 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
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/********************************************************************
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* A wrapper function to call the analysis SDC generator of FPGA-SDC
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*******************************************************************/
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int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
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int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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@ -15,7 +15,7 @@
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/* begin namespace openfpga */
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namespace openfpga {
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int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
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int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
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@ -24,7 +24,7 @@ int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
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int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
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int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context);
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} /* end namespace openfpga */
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@ -72,7 +72,7 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to constrain the backend flow for FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_pnr_sdc);
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shell.set_command_const_execute_function(shell_cmd_id, write_pnr_sdc);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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@ -178,7 +178,7 @@ ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaC
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_analysis_sdc);
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shell.set_command_const_execute_function(shell_cmd_id, write_analysis_sdc);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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