bug fixed in SDC timing writer for primitive pb_type
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@ -397,34 +397,34 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
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print_sdc_timescale(fp, time_unit_to_string(time_unit));
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/* We traverse the pb_graph pins where we can find pin-to-pin timing annotation
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* We walk through output pins here, build timing constraints by pair each output to input
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* We walk through input pins here, build timing constraints by pair each input to output
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* Because VPR keeps all the timing values in pin_timing data structure instead of pb_graph_pin edges
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* Clock pins are not walked through because they will be handled by clock tree synthesis
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*/
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for (int iport = 0; iport < logical_primitive_pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < logical_primitive_pb_graph_node->num_output_pins[iport]; ++ipin) {
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t_pb_graph_pin* sink_pin = &(logical_primitive_pb_graph_node->output_pins[iport][ipin]);
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for (int iport = 0; iport < logical_primitive_pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < logical_primitive_pb_graph_node->num_input_pins[iport]; ++ipin) {
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t_pb_graph_pin* src_pin = &(logical_primitive_pb_graph_node->input_pins[iport][ipin]);
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/* Port must exist in the module graph */
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ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, sink_pin->port));
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VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, sink_module_port_id));
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BasicPort sink_port = module_manager.module_port(pb_module, sink_module_port_id);
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ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, src_pin->port));
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VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, src_module_port_id));
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BasicPort src_port = module_manager.module_port(pb_module, src_module_port_id);
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/* Set the correct pin number of the port */
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sink_port.set_width(sink_pin->pin_number, sink_pin->pin_number);
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src_port.set_width(src_pin->pin_number, src_pin->pin_number);
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/* Find all the sink pin from this source pb_graph_pin */
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for (int iedge = 0; iedge < sink_pin->num_input_edges; ++iedge) {
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VTR_ASSERT(1 == sink_pin->input_edges[iedge]->num_input_pins);
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t_pb_graph_pin* src_pin = sink_pin->input_edges[iedge]->input_pins[0];
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for (int itiming = 0; itiming < src_pin->num_pin_timing; ++itiming) {
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t_pb_graph_pin* sink_pin = src_pin->pin_timing[itiming];
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/* Port must exist in the module graph */
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ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, src_pin->port));
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VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, src_module_port_id));
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BasicPort src_port = module_manager.module_port(pb_module, src_module_port_id);
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ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, sink_pin->port));
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VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, sink_module_port_id));
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BasicPort sink_port = module_manager.module_port(pb_module, sink_module_port_id);
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/* Set the correct pin number of the port */
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src_port.set_width(src_pin->pin_number, src_pin->pin_number);
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sink_port.set_width(sink_pin->pin_number, sink_pin->pin_number);
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/* Find max delay between src and sink pin */
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float tmax = sink_pin->input_edges[iedge]->delay_max;
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float tmax = src_pin->pin_timing_del_max[itiming];
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/* Generate module path in hierarchy depending if the hierarchical is enabled */
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std::string module_hie_path = pb_module_name;
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@ -434,7 +434,7 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
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/* If the delay is zero, constrain only when user wants it */
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if ( (true == constrain_zero_delay_paths)
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|| (0. == tmax) ) {
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|| (0. != tmax) ) {
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print_pnr_sdc_constrain_max_delay(fp,
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module_hie_path,
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generate_sdc_port(src_port),
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@ -444,10 +444,10 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
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}
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/* Find min delay between src and sink pin */
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float tmin = sink_pin->input_edges[iedge]->delay_min;
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float tmin = src_pin->pin_timing_del_min[itiming];
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/* If the delay is zero, constrain only when user wants it */
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if ( (true == constrain_zero_delay_paths)
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|| (0. == tmin) ) {
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|| (0. != tmin) ) {
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print_pnr_sdc_constrain_min_delay(fp,
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module_hie_path,
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generate_sdc_port(src_port),
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