add a microbenchmark `and_latch` to test LUTs in wired mode

openfpga/test_blif/and_latch.act

@@ -0,0 +1,5 @@
+a 0.492800 0.201000
+b 0.502000 0.197200
+clk 0.500000 2.000000
+d 0.240200 0.171200
+c 0.240200 0.044100

openfpga/test_blif/and_latch.blif

@@ -0,0 +1,11 @@
+# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020
+.model top
+.inputs a b clk
+.outputs c d
+
+.latch c d  re clk 0
+
+.names a b c
+11 1
+
+.end

openfpga/test_blif/and_latch.v

@@ -0,0 +1,23 @@
+`timescale 1ns / 1ps
+
+module top(
+  clk,
+  a,
+  b,
+  c,
+  d);
+
+input wire clk;
+
+input wire a;
+input wire b;
+output wire c;
+output reg d;
+
+assign c = a & b;
+
+always @(posedge clk) begin
+  d <= c;
+end
+
+endmodule

openfpga/test_script/and_k6_frac.openfpga

@@ -1,4 +1,4 @@
-# Run VPR for the s298 design
+# Run VPR for the 'and' design
 vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
 
 # Read OpenFPGA architecture definition

openfpga/test_script/and_latch_k6_frac.openfpga

@@ -0,0 +1,59 @@
+# Run VPR for the 'and_latch' design
+vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit