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fix bugs in flow manager on default compress routing problems

This commit is contained in:
tangxifan 2020-03-22 15:26:15 -06:00
parent fc6abc13fd
commit 3958ac2494
6 changed files with 15 additions and 3 deletions
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2
openfpga/src/base/openfpga_build_fabric.cpp
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@ -65,6 +65,8 @@ void build_fabric(OpenfpgaContext& openfpga_ctx,
if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
compress_routing_hierarchy(openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
/* Update flow manager to enable compress routing */
openfpga_ctx.mutable_flow_manager().set_compress_routing(true);
}
VTR_LOG("\n");

8
openfpga/src/base/openfpga_flow_manager.cpp
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@ -8,6 +8,14 @@
/* begin namespace openfpga */
namespace openfpga {
/**************************************************
* Public Constructor
*************************************************/
FlowManager::FlowManager() {
/* Turn off compress_routing as default */
compress_routing_ = false;
}
/**************************************************
* Public Accessors
*************************************************/

2
openfpga/src/base/openfpga_flow_manager.h
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@ -15,6 +15,8 @@ namespace openfpga {
*
*******************************************************************/
class FlowManager {
public: /* Public constructor */
FlowManager();
public: /* Public accessors */
bool compress_routing() const;
public: /* Public mutators */

2
openfpga/test_script/and_k6_frac_adder_chain.openfpga
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@ -25,7 +25,7 @@ lut_truth_table_fixup #--verbose
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin #--verbose
build_fabric --compress_routing --duplicate_grid_pin --verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation

2
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
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@ -161,7 +161,7 @@
<!-- Physical descriptions begin -->
<layout tileable="true">
<!--auto_layout aspect_ratio="1.0"-->
<fixed_layout name="2x2" width="4" height="4">
<fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>

2
vpr/src/tileable_rr_graph/rr_gsb.cpp
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@ -975,7 +975,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
/* Use unsorted/sorted edges */
std::vector<RREdgeId> node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id);
std::vector<RREdgeId> cand_node_in_edges = cand. get_chan_node_in_edges(rr_graph, node_side, track_id);
std::vector<RREdgeId> cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id);
VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {