From 3958ac24948cac78791d2ac6233a64ed9771a577 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 22 Mar 2020 15:26:15 -0600
Subject: [PATCH] fix bugs in flow manager on default compress routing problems

---
 openfpga/src/base/openfpga_build_fabric.cpp             | 2 ++
 openfpga/src/base/openfpga_flow_manager.cpp             | 8 ++++++++
 openfpga/src/base/openfpga_flow_manager.h               | 2 ++
 openfpga/test_script/and_k6_frac_adder_chain.openfpga   | 2 +-
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml | 2 +-
 vpr/src/tileable_rr_graph/rr_gsb.cpp                    | 2 +-
 6 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 9e315500c..97c0c68be 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -65,6 +65,8 @@ void build_fabric(OpenfpgaContext& openfpga_ctx,
   
   if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
     compress_routing_hierarchy(openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
+    /* Update flow manager to enable compress routing */
+    openfpga_ctx.mutable_flow_manager().set_compress_routing(true);
   }
 
   VTR_LOG("\n");
diff --git a/openfpga/src/base/openfpga_flow_manager.cpp b/openfpga/src/base/openfpga_flow_manager.cpp
index bc97f291d..1a50524df 100644
--- a/openfpga/src/base/openfpga_flow_manager.cpp
+++ b/openfpga/src/base/openfpga_flow_manager.cpp
@@ -8,6 +8,14 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/**************************************************
+ * Public Constructor
+ *************************************************/
+FlowManager::FlowManager() {
+  /* Turn off compress_routing as default */
+  compress_routing_ = false;
+}
+
 /**************************************************
  * Public Accessors 
  *************************************************/
diff --git a/openfpga/src/base/openfpga_flow_manager.h b/openfpga/src/base/openfpga_flow_manager.h
index 6a6ae7c75..e9f6f02c2 100644
--- a/openfpga/src/base/openfpga_flow_manager.h
+++ b/openfpga/src/base/openfpga_flow_manager.h
@@ -15,6 +15,8 @@ namespace openfpga {
  *
  *******************************************************************/
 class FlowManager {
+  public: /* Public constructor */
+    FlowManager();
   public: /* Public accessors */
     bool compress_routing() const;
   public: /* Public mutators */
diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
index d151b0089..3cdebb2b1 100644
--- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
@@ -25,7 +25,7 @@ lut_truth_table_fixup #--verbose
 # Build the module graph 
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
+build_fabric --compress_routing --duplicate_grid_pin --verbose
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index c3598bd2b..eea76837f 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -161,7 +161,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="4" height="4">
+    <fixed_layout name="4x4" width="6" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index b489182b2..f5d6ec6ca 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -975,7 +975,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
 
   /* Use unsorted/sorted edges */
   std::vector<RREdgeId> node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id);
-  std::vector<RREdgeId> cand_node_in_edges = cand. get_chan_node_in_edges(rr_graph, node_side, track_id);
+  std::vector<RREdgeId> cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id);
   VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
 
   for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {